Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor PlatformsSpringer Science & Business Media, 2006. gada 25. aug. - 186 lappuses We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor. |
No grāmatas satura
1.–5. rezultāts no 63.
xi. lappuse
... implemented as a fixed functionality computational element and of a software implementation on a processor. We argue that future SoC for wireless and multimedia applications will be implemented as heterogeneous multiprocessor systems ...
... implemented as a fixed functionality computational element and of a software implementation on a processor. We argue that future SoC for wireless and multimedia applications will be implemented as heterogeneous multiprocessor systems ...
1. lappuse
... implemented on Printed Circuit Boards (PCBs). PCB systems are composed of discrete Integrated Circuits (ICs) like ... implementations of embedded applications. According to the International Technology Roadmap for Semi- conductors [2] ...
... implemented on Printed Circuit Boards (PCBs). PCB systems are composed of discrete Integrated Circuits (ICs) like ... implementations of embedded applications. According to the International Technology Roadmap for Semi- conductors [2] ...
2. lappuse
... implemented as dedicated HW blocks and the rest is executed in SW, is no longer applicable [6]. Instead HW/SW Co-design can be seen as a multi-dimensional horizontal mapping problem of an application running on a heterogeneous ...
... implemented as dedicated HW blocks and the rest is executed in SW, is no longer applicable [6]. Instead HW/SW Co-design can be seen as a multi-dimensional horizontal mapping problem of an application running on a heterogeneous ...
3. lappuse
... implemented in hardware to efficiently share the processing resources among multiple concurrent tasks. In analogy with full scale software operating systems (SW-OS), the HW-MT concept bears the potential to bring a disciplined ...
... implemented in hardware to efficiently share the processing resources among multiple concurrent tasks. In analogy with full scale software operating systems (SW-OS), the HW-MT concept bears the potential to bring a disciplined ...
7. lappuse
... implementation of the timing model by means of a versatile system level Design Space Exploration (DSE) environment for MP-SoC platforms is described in chapter 8. Major components of this framework are the Network- on-Chip framework for ...
... implementation of the timing model by means of a versatile system level Design Space Exploration (DSE) environment for MP-SoC platforms is described in chapter 8. Major components of this framework are the Network- on-Chip framework for ...
Saturs
9 | |
CLASSIFICATION OF PLATFORM ELEMENTS | 15 |
SYSTEM LEVEL DESIGN PRINCIPLES | 33 |
RELATED WORK | 43 |
METHODOLOGY OVERVIEW | 59 |
UNIFIED TIMING MODEL | 79 |
MPSOC SIMULATION FRAMEWORK | 113 |
CASE STUDY | 141 |
SUMMARY | 153 |
B The OCPIP TL3 Channel | 163 |
List of Figures | 171 |
List of Tables | 175 |
About the Authors | 195 |
Citi izdevumi - Skatīt visu
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor ... Tim Kogel,Rainer Leupers,Heinrich Meyr Priekšskatījums nav pieejams - 2006 |
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor ... Tim Kogel,Rainer Leupers,Heinrich Meyr Priekšskatījums nav pieejams - 2010 |
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor ... Tim Kogel,Rainer Leupers,Heinrich Meyr Priekšskatījums nav pieejams - 2009 |
Bieži izmantoti vārdi un frāzes
Abstract Data Types abstraction levels algorithm application domain application model arbitration architecture models Automation Conference DAC bandwidth Based Design blocks bus architectures CEFSM Co-design communication architecture Communication Node complex configuration CoWare crossbar cycle-level TLM data-plane processing defined denotes depicted in figure Design Automation Conference design space exploration DiffServ efficiency embedded applications Embedded Systems enables engine execution FIFO Functional Process hardware heterogeneous HW/SW IEEE implementation Initiator input signals IPv4 ISO/OSI reference model latency layer metrics module MP-SoC platform multi-processor multi-threaded Network Processor Network-on-Chip NoC framework on-chip communication on-chip networks OSCI output signal packet packet switch packet-level paradigm parameters performance Proc processing delay processing elements processor protocol queuing Reactive Process Network requirements RWTH Aachen simulation speed Software switches synchronization interface Synthesis system architect System Level Design System-on-Chip SystemC target throughput TL3 API topology Virtual Architecture Mapping VPU Node