Languages and Compilers for Parallel Computing: 15th Workshop, LCPC 2002, College Park, MD, USA, July 25-27, 2002, Revised PapersThe 15th Workshop on Languages and Compilers for Parallel Computing was held in July 2002 at the University of Maryland, College Park. It was jointly sponsored by the Department of Computer Science at the University of Ma- land and the University of Maryland Institute for Advanced Computer Studies (UMIACS).LCPC2002broughttogetherover60researchersfromacademiaand research institutions from many countries. The program of 26 papers was selected from 32 submissions. Each paper was reviewed by at least three Program Committee members and sometimes by additional reviewers. Prior to the workshop, revised versions of accepted papers were informally published on the workshops website and in a paper proceedings that was distributed at the meeting. This year, the workshopwas organizedinto sessions of papers on related topics, and each session consisted of two to three 30-minute presentations.Based on feedback from the workshop,the papers were revised and submitted for inclusion in the formal proceedings published in this volume. Two papers were presented at the workshop but later withdrawn from the ?nal proceedings by their authors. We were very lucky to have Bill Carlson from the Department of Defense give the LCPC 2002 keynote speech on UPC: A C Language for Shared M- ory Parallel Programming. Bill gave an excellent overview of the features and programming model of the UPC parallel programming language. |
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Saturs
MemoryConstrained Communication Minimization for a Class of Array Computations | 1 |
Forward Communication Only Placements and Their Use for Parallel Program Construction | 16 |
Hierarchical Parallelism Control for Multigrain Parallel Processing | 31 |
Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors | 45 |
Automatic Detection of Saturation and Clipping Idioms | 61 |
Compiler Optimizations with DSPSpecific Semantic Descriptions | 75 |
Combining Performance Aspects of Irregular GaussSeidel Via Sparse Tiling | 90 |
A Hybrid Strategy Based on Data Distribution and Migration for Optimizing Memory Locality | 111 |
Adaptively Increasing Performance and Scalability of Automatically Parallelized Programs | 203 |
A Language Construct for Developing Dynamic Applications | 218 |
Optimizing the Java Piped IO Stream Library for Performance | 233 |
A Comparative Study of Stampede Garbage Collection Algorithms | 249 |
Compiler and Runtime Support for Shared Memory Parallelization of Data Mining Algorithms | 265 |
Performance Analysis of Symbolic Analysis Techniques for Parallelizing Compilers | 280 |
Efficient Manipulation of Disequalities During Dependence Analysis | 295 |
Removing Impediments to Loop Fusion Through Code Transformations | 309 |
Compiler Optimizations Using Data Compression to Decrease Address Reference Entropy | 126 |
Towards Compiler Optimization of Codes Based on Arrays of Pointers | 142 |
An Empirical Study on the Granularity of Pointer Analysis in C Programs | 157 |
Automatic Implementation of Programming Language Consistency Models | 172 |
An Application of Adaptive Algorithm Selection | 188 |
NearOptimal Padding for Removing Conflict Misses | 329 |
FineGrain Stacked Register Allocation for the Itanium Architecture | 344 |
Evaluating Iterative Compilation | 362 |
377 | |
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adaptive algorithm alloc alloc instruction allow analysis application approach architecture array average basic benchmarks block cache called communication compared compiler compression computation consider consistency constraints cost data structures dependence described Design determine directives distribution dynamic elements estimation evaluation example execution experiments expression Figure first function give given graph implementation improve input inserted instance instructions iteration Java Languages locality loop loop fusion matrix memory method miss naming nests node object operations optimization overhead padding parallel parallel loops partitioning path pattern performance pointer possible presented problem processing processors propagation proposed range reduction reference registers represents run-time scheme selected selector sequential shared shown shows single space sparse tiling speedup statement static step strategy structure symbolic Table techniques thread tiling tion transformations variable