Network Performance Modeling and SimulationJean Walrand, Kallol Bagchi, George Zobrist CRC Press, 2019. gada 16. aug. - 332 lappuses This book makes the argument that performance modeling and simulation have become central issues in computer science and engineering, in part due to applications to the structures comprising the Internet. Dealing primarily with theory, tools and techniques as related to communications systems, the volume provides tutorials and surveys and relates new important research results. Each chapter presents background information, describes and analyzes important work done in the field and provides direction to the reader on future work and further readings. The topics covered include traffic models for A TM networks, simulation environments, analytical methods, interprocessor communications, and an evaluation of process architectures. |
No grāmatas satura
1.5. rezultāts no 42.
7. lappuse
... switch elements which can be set up dynamically according to traffic requests . Processing nodes ( or memory ) are located at the ends of the MIN , and traffic is routed from one end so ( b ) Butterfly network ( c ) Baseline. WORMHOLE ...
... switch elements which can be set up dynamically according to traffic requests . Processing nodes ( or memory ) are located at the ends of the MIN , and traffic is routed from one end so ( b ) Butterfly network ( c ) Baseline. WORMHOLE ...
8. lappuse
... switch fabrics and interstage connections have been proposed for different MIN99,21 . Some examples are the Omega ( or Shuffle - Exchange ) , Butterfly , Baseline networks , etc. ( Fig . 1.6 ) We should note that some multi - stage ...
... switch fabrics and interstage connections have been proposed for different MIN99,21 . Some examples are the Omega ( or Shuffle - Exchange ) , Butterfly , Baseline networks , etc. ( Fig . 1.6 ) We should note that some multi - stage ...
10. lappuse
... switches and 1x8 demux . A 3 - stage 512 X 512 butterfly network constructed by 8 x 8 switches . 32 to 1024 processors ( max . 16384 proc ) bisection width of 1024 nodes is 5GB / s 2 levels of ALLCACHE Engine hierarchy with the fat tree ...
... switches and 1x8 demux . A 3 - stage 512 X 512 butterfly network constructed by 8 x 8 switches . 32 to 1024 processors ( max . 16384 proc ) bisection width of 1024 nodes is 5GB / s 2 levels of ALLCACHE Engine hierarchy with the fat tree ...
11. lappuse
... switches only . But a dynamic network can also be a direct network ; for example , the reconfigurable mesh may change its connections to the neighbors while all the nodes are the processing units . Similarly , a static network can be ...
... switches only . But a dynamic network can also be a direct network ; for example , the reconfigurable mesh may change its connections to the neighbors while all the nodes are the processing units . Similarly , a static network can be ...
27. lappuse
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Saturs
| 1 | |
2 Reusability Techniques for Building a Simulation Environment and Modeling Communications Systems | 39 |
An Overview and an Example of Application | 59 |
4 Traffic Modeling for ATM Networks | 105 |
5 An Overview of Source Characterization in ATM Networks | 123 |
6 Procedures for Estimating and Guaranteeing Delays in High Speed Communication Networks | 151 |
7 BMAP Modeling of a Correlated Queue | 177 |
8 Hierarchical Performance Modeling of Computer Communication Systems | 197 |
9 A Framework for Measuring the Performance of Alternative Process Architectures for Parallelizing Communication Systems | 219 |
A Prototyping and Modeling Tool for Communication Networks and Protocols | 255 |
11 Network Reliability Evaluation | 275 |
Notes on the Contributors | 303 |
Author Index | 311 |
Subject Index | 313 |
Citi izdevumi - Skatīt visu
Network Performance Modeling and Simulation Jean Walrand,Kallol Bagchi,George Zobrist Ierobežota priekšskatīšana - 1998 |
Network Performance Modeling and Simulation Jean Walrand,Kallol Bagchi,George Zobrist Ierobežota priekšskatīšana - 2019 |
Bieži izmantoti vārdi un frāzes
adaptive aggregate algorithm analysis application approach approximation arrival associated batch behavior bound buffer called cell channel chapter color communication complete components Computer Condition connection consider context corresponding customers defined delay dependency described direct distribution equal evaluation example execution extended Figure flow frame function given graph GSPN IEEE immediate implemented increases input instance interarrival interface interval Italy layer length mean measured messages method Module nodes objects observed obtained operation output packet Parallelism parameters path performance period possible present probability process architectures protocol stack queue reduction reliability represents respect routing rule selection server shown shows simulation single solution specific station step Stream structure submodel SunOS switch synchronization tasks techniques tokens traffic transitions University virtual waiting