VHDL: Hardware Description and DesignSpringer Science & Business Media, 1989. gada 30. jūn. - 299 lappuses VHDL is a comprehensive language that allows a user to deal with design complexity. Design, and the data representing a design, are complex by the very nature of a modern digital system constructed from VLSI chips. VHDL is the first language to allow one to capture all the nuances of that complexity, and to effectively manage the data and the design process. As this book shows, VHDL is not by its nature a complex language. In 1980, the U. S. Government launched a very aggressive effort to advance the state-of-the-art in silicon technology. The objective was to significantly enhance operating performance and circuit density for Very Large Scale Integration (VLSI) silicon chips. The U. S. Government realized that in order for contractors to be able to work together to develop VLSI products, to document the resulting designs, to be able to reuse the designs in future products, and to efficiently upgrade existing designs, they needed a common communication medium for the design data. They wanted the design descriptions to be computer readable and executable. They also recognized that with the high densities envisioned for the U. S. Government's Very High Speed Integrated Circuit (VHSIC) chips and the large systems required in future procurements, a means of streamlining the design process and managing the large volumes of design data was required. Thus was born the concept of a standard hardware design and description language to solve all of these problems. |
Saturs
Introduction | 1 |
A Model of Hardware | 7 |
Basics | 17 |
Scalar Types | 45 |
Aggregates and String Literals | 51 |
Attributes | 58 |
Behavioral Description | 65 |
Iterative Control | 84 |
Large Scale Design | 145 |
A Complete Example | 177 |
Advanced Features | 209 |
VHDL in Use | 233 |
Appendix A Predefined Environment | 261 |
Appendix B VHDL Syntax | 273 |
Suggested Reading | 293 |
Structural Description | 107 |
Citi izdevumi - Skatīt visu
VHDL: Hardware Description and Design Roger Lipsett,Carl F. Schaefer,Cary Ussery Ierobežota priekšskatīšana - 2012 |
VHDL: Hardware Description and Design Roger Lipsett,Carl F. Schaefer,Cary Ussery Priekšskatījums nav pieejams - 2012 |
VHDL: Hardware Description and Design Roger Lipsett,Carl F. Schaefer,Cary Ussery Priekšskatījums nav pieejams - 1989 |
Bieži izmantoti vārdi un frāzes
And2 port architecture body assertion statement association list attribute returns Base_logic binding indication Bit_vector block statement Boolean buffer Chapter circuit clause component declaration component instantiation statement concurrent signal assignment configuration declaration configuration specification constant constraint data pathway data types Data_Type default defined Delay design entity device Device_1 discrete system discussed downto driver element elsif end component end process end record entity declaration enumeration types example execution expression floating point hardware description language Highway_Light_Green identifier implementation inout LINE input Integer interface list Intermetrics language logic object operand operations output package body package declaration parameter port map predefined Present_State PRESET process begin process statement range reserved word resolution function resolved signal result signal assignment statement signal declaration Start_Timer string literal structural subcomponent subprogram systolic array Three_level_logic Timed_Out_Short timer traffic light controller transaction transport TriState type conversion type declaration variable VHSIC visible wait statement waveform