Comprehensive Functional Verification: The Complete Industry CycleMorgan Kaufmann, 2005. gada 26. maijs - 676 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals. As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
1.–5. rezultāts no 91.
xiii. lappuse
... Verification Beyond the Scope of this Book The Verification Cycle : A Structured Process Functional Specification 23 THE 222 22 12 14 18 20 24 25 1.6.2 Create Verification Plan 26 • 1.6.3 Develop Environment 27 1.6.4 Debug HDL and ...
... Verification Beyond the Scope of this Book The Verification Cycle : A Structured Process Functional Specification 23 THE 222 22 12 14 18 20 24 25 1.6.2 Create Verification Plan 26 • 1.6.3 Develop Environment 27 1.6.4 Debug HDL and ...
xiv. lappuse
... Verification Flow 2.1 Verification Hierarchy 2.1.1 Levels of Verification 2.1.2 What Level to Choose ? Strategy of Verification ... Plan 89 90 92 • 94 95 95 97 101 102 103 4.1 The Functional Specification 103 4.2 4.3 The Evolution of the ...
... Verification Flow 2.1 Verification Hierarchy 2.1.1 Levels of Verification 2.1.2 What Level to Choose ? Strategy of Verification ... Plan 89 90 92 • 94 95 95 97 101 102 103 4.1 The Functional Specification 103 4.2 4.3 The Evolution of the ...
xv. lappuse
... Coverage Requirements 115 4.3.7 Test Case Scenarios : Matrix 116 4.3.8 Resource Requirements 117 • 4.3.9 Schedule Details 118 4.4 Verification Example : Calc1 121 4.4.1 Design Description 121 4.4.2 Creating the Verification Plan for ...
... Coverage Requirements 115 4.3.7 Test Case Scenarios : Matrix 116 4.3.8 Resource Requirements 117 • 4.3.9 Schedule Details 118 4.4 Verification Example : Calc1 121 4.4.1 Design Description 121 4.4.2 Creating the Verification Plan for ...
xvi. lappuse
... Coverage Bulk Data Collection and Management 254 6.2.6 The Right Coverage Analysis Strategy 255 6.3 Summary 256 6.4 Exercises 258 7 Strategies for Simulation - Based Stimulus Generation 259 7.1 Calc2 Overview 260 7.1.1 Calc2 Verification ...
... Coverage Bulk Data Collection and Management 254 6.2.6 The Right Coverage Analysis Strategy 255 6.3 Summary 256 6.4 Exercises 258 7 Strategies for Simulation - Based Stimulus Generation 259 7.1 Calc2 Overview 260 7.1.1 Calc2 Verification ...
xxii. lappuse
Atvainojiet, šīs lappuses saturs ir ierobežots..
Atvainojiet, šīs lappuses saturs ir ierobežots..
Saturs
INTRODUCTION TO VERIFICATION | 3 |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
663 | |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example execution Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet parameters performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL