Network Processor Design: Issues and PracticesMark A. Franklin, Patrick Crowley, Haldun Hadimioglu, Peter Z. Onufryk Elsevier, 2005. gada 11. marts - 336 lappuses The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors. Through chapters on hardware, software, performance and modeling, Network Processor Design illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors. Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.
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1.5. rezultāts no 32.
... Runtime System 168 References 169 9 RNOSA Middleware Platform for Low-Cost Packet-Processing Devices 9.1 9.2 9.3 173 Jonas Greutert, Lothar Thiele 174 Analysis Model of RNOS 175 9.2.1 Application Model 176 9.2.2 Input ModelSLA, Flows ...
... run-time system that monitors performance and power consumption to adjust resource allocation to meet the respective targets. A middleware platform and application analysis methodology is presented in Chapter 9. Real-time calculus is ...
... Run-time system Network system hardware. APPLICATIONS. As application areas for network processors continue to expand beyond traditional router line cards, there exists a growing trend toward more stateful packet processing, driven by ...
... runtime. In fact, on the Intel IXP the source code for all the programs in all the threads to be run on a data processor is compiled together to form a single binary instruction image, which is loaded by the control processor into the ...
... run-time (both for these statically-composed threads as well as dynamically-composed scenarios), providing sharing between segments (e.g., for shared code libraries), and exploring the use of segmentation in data caches. REFERENCES.
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Chapter 4 Towards a Flexible Network Processor Interface for RapidIO Hypertransport and PCIExpress | 55 |
Chapter 5 A HighSpeed Multithreaded TCP Offload Engine for 10 Gbs Ethernet | 81 |
Chapter 6 A Hardware Platform for Network Intrusion Detection and Prevention | 99 |
Chapter 7 Packet Processing on a SIMD Stream Processor | 119 |
Design Considerations | 145 |
Chapter 9 RNOSA Middleware Platform for LowCost PacketProcessing Devices | 173 |
Chapter 10 On the Feasibility of Using Network Processors for DNA Queries | 197 |
Chapter 11 Pipeline Task Scheduling on Network Processors | 219 |
Chapter 12 A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs | 245 |
Chapter 13 Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures | 279 |
Index | 309 |
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Network Processor Design: Issues and Practices, 3. sējums Mark A. Franklin,Patrick Crowley,Haldun Hadimioglu Priekšskatījums nav pieejams - 2005 |