Network Processor Design: Issues and PracticesMark A. Franklin, Patrick Crowley, Haldun Hadimioglu, Peter Z. Onufryk Elsevier, 2005. gada 11. marts - 336 lappuses The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors. Through chapters on hardware, software, performance and modeling, Network Processor Design illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors. Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.
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No grāmatas satura
1.–5. rezultāts no 78.
... Interface for RapidIO, Hypertransport, and PCI-Express 4.1 Christian Sauer, Matthias Gries, Kurt Keutzer, Jose Ignacio Gomez Interface Fundamentals and Comparison 57 4.1.1 Functional Layers 57 Common Tasks 59 Modeling the Interfaces 59 ...
... Interface 104 Hardware Platform 104 6.2.2 Snort Hardware Implementation 106 6.2.3 6.2.4 6.2.5 Network Interface to Host 107 Pattern Matching on the FPGA Coprocessor 109 Reusable IXP Libraries 110 6.3 Evaluation and Results 110 6.3.1 ...
... interfaces and explores the idea of implement- ing them in software on a multithreaded packet-processing engine ... interface hardware. Finally, Chapter 10 investigates the use of network processors for an application that is not in ...
... interface that should be used, given the flow identifier. Hashing the flow identifier allows traditional network processors to determine what operation or forwarding interface should be used while examining only a couple of entries in ...
... interfaces and a set of classification rules , R. We begin by assuming that we have 64 KB of memory to devote to the cache and wish to have a four - way associative cache that has a misclassification probability of one in a billion ...
Saturs
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33 | |
Chapter 4 Towards a Flexible Network Processor Interface for RapidIO Hypertransport and PCIExpress | 55 |
Chapter 5 A HighSpeed Multithreaded TCP Offload Engine for 10 Gbs Ethernet | 81 |
Chapter 6 A Hardware Platform for Network Intrusion Detection and Prevention | 99 |
Chapter 7 Packet Processing on a SIMD Stream Processor | 119 |
Design Considerations | 145 |
Chapter 9 RNOSA Middleware Platform for LowCost PacketProcessing Devices | 173 |
Chapter 10 On the Feasibility of Using Network Processors for DNA Queries | 197 |
Chapter 11 Pipeline Task Scheduling on Network Processors | 219 |
Chapter 12 A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs | 245 |
Chapter 13 Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures | 279 |
Index | 309 |
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Network Processor Design: Issues and Practices, 3. sējums Mark A. Franklin,Patrick Crowley,Haldun Hadimioglu Priekšskatījums nav pieejams - 2005 |