Network Processor Design: Issues and PracticesMark A. Franklin, Patrick Crowley, Haldun Hadimioglu, Peter Z. Onufryk Elsevier, 2005. gada 11. marts - 336 lappuses The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors. Through chapters on hardware, software, performance and modeling, Network Processor Design illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors. Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.
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1.–5. rezultāts no 30.
... IPv4 Forwarding 131 7.3.1 Design Methodology and Implementation Details 132 7.3.2 Experiments 134 7.3.3 IPv4 Performance Summary 138 7.4 Related Work 139 7.5 Conclusions and Future Work 140 Acknowledgments 142 References 142 8 A ...
... IPv4 2000 1500 1000 500 Exact cache , IPv6 0 0 2 4 5 6 7 8 3 Amount of memory , M ( in KB ) Comparison of storage capacity of various caching schemes . The Bloom filter cache assumes a misidentification probability of one in a billion ...
... IPv4 flow identifiers will be able to store 4852 entries , and a cache storing IPv6 flow identifiers will be able to store 1744 entries . The benefit of using a digest cache is two - fold . First , it increases the effective storage ...
... IPv4- and IPv6 - based hash tables . Each lookup and insertion operation requires a single 52 - byte or 148 - byte memory request , respectively . Hashing for all results presented here was accomplished with a SHA - 1 [ 26 ] hash . It ...
... ( IPv4 4 - way associative ) Exact cache ( IPv6 4 - way associative ) Perfect cache 10,000 Amount of cache memory ( bytes ) ར ར Digest cache ( 4 - way associative ) Bloom cache ( Cold ) bloom Cache ( double buffered ) Exact cache ( IPv4 4 ...
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9 | |
33 | |
Chapter 4 Towards a Flexible Network Processor Interface for RapidIO Hypertransport and PCIExpress | 55 |
Chapter 5 A HighSpeed Multithreaded TCP Offload Engine for 10 Gbs Ethernet | 81 |
Chapter 6 A Hardware Platform for Network Intrusion Detection and Prevention | 99 |
Chapter 7 Packet Processing on a SIMD Stream Processor | 119 |
Design Considerations | 145 |
Chapter 9 RNOSA Middleware Platform for LowCost PacketProcessing Devices | 173 |
Chapter 10 On the Feasibility of Using Network Processors for DNA Queries | 197 |
Chapter 11 Pipeline Task Scheduling on Network Processors | 219 |
Chapter 12 A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs | 245 |
Chapter 13 Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures | 279 |
Index | 309 |
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Network Processor Design: Issues and Practices, 3. sējums Mark A. Franklin,Patrick Crowley,Haldun Hadimioglu Priekšskatījums nav pieejams - 2005 |