Turbo Codes: Desirable and DesignableSpringer Science & Business Media, 2003. gada 31. dec. - 150 lappuses PREFACE The increasing demand on high data rate and quality of service in wireless communication has to cope with limited bandwidth and energy resources. More than 50 years ago, Shannon has paved the way to optimal usage of bandwidth and energy resources by bounding the spectral efficiency vs. signal to noise ratio trade-off. However, as any information theorist, Shannon told us what is the best we can do but not how to do it [1]. In this view, turbo codes are like a dream come true: they allow approaching the theoretical Shannon capacity limit very closely. However, for the designer who wants to implement these codes, at first sight they appear to be a nightmare. We came a huge step closer in striving the theoretical limit, but see the historical axiom repeated on a different scale: we know we can achieve excellent performance with turbo codes, but not how to realize this in real devices. |
Saturs
TURBO CODES Introducing the communication problem they solve and the implementation problem they create | 3 |
from simple engines to turbo | 4 |
from transistors to 4G radios | 6 |
114 The implementation problem and goals | 7 |
DESIRABLE CHANNEL CODING SOLUTIONS | 8 |
an essential ingredient in digital communication systems | 10 |
the basics | 11 |
123 Concatenated codes | 17 |
36 CONCLUSIONS | 80 |
DEMYSTIFYING THE FANGBUDA ALGORITHM Boosting the block turbo decoding | 83 |
42 SOFT DECODING OF ALGEBRAIC CODES | 85 |
422 The Chase algorithm | 88 |
423 The FangBuda Algorithm FBA | 89 |
43 FBA OPTIMIZATION AND ARCHITECTURE DERIVATION | 92 |
432 Data and control flow transformations | 93 |
433 Data Reuse Decision and Storage Cycle Budget Distribution | 95 |
124 Parallel concatenated convolutional turbo codes | 18 |
125 Decoding parallel concatenated Turbo codes | 20 |
126 Serially concatenated block codes | 28 |
13 CONCLUSIONS | 29 |
14 REFERENCES | 30 |
DESIGN METHODOLOGY THE STRATEGIC PLAN Getting turbocodes implemented at maximum performancecost | 31 |
22 ALGORITHMIC EXPLORATION | 33 |
23 DATA TRANSFER AND STORAGE EXPLORATION | 34 |
24 FROM ARCHITECTURE TO SILICON INTEGRATION | 35 |
26 REFERENCES | 39 |
CONQUERING THE MAP Removing the main bottleneck of convolutional turbo decoders | 41 |
32 THE MAP DECODING ALGORITHM FOR CONVOLUTIONAL TURBO CODES | 42 |
LOGMAX MAP | 53 |
34 TRELLIS TERMINATION IN CONVOLUTIONAL TURBO CODES | 58 |
341 No termination | 59 |
342 Single termination | 60 |
343 Double termination | 61 |
SYSTEMATIC APPROACH | 62 |
351 MAP bottlenecks | 63 |
353 Storage Cycle Budget Distribution | 70 |
354 Memory organization | 76 |
434 Memory allocation and assignment | 98 |
44 FBABASED ETC DECODER PERFORMANCE | 101 |
45 CONCLUSIONS | 105 |
MASTERING THE INTERLEAVER Divide and Conquer | 107 |
52 BASIC ELEMENTS OF THE INTERLEAVER | 109 |
53 COLLISIONFREE INTERLEAVERS | 111 |
THE 3GPPINTERLEAVER AND A 3GPP COLLISIONFREE INTERLEAVER | 115 |
541 Improving the spreading properties of collisionfree interleavers | 117 |
COLLISIONFREE INTERLEAVING AND DEINTERLEAVING | 120 |
56 REFERENCES | 122 |
TMPO CODEC From theory to real life silicon | 123 |
62 POSITIONING ONESELF IN THE OPTIMAL PERFORMANCESPEEDCOST SPACE | 124 |
63 DESIGN FLOW | 128 |
64 DECODER FINAL ARCHITECTURE | 130 |
65 SYNTHESIS RESULTS | 133 |
66 MEASUREMENTS RESULTS | 135 |
68 REFERENCES | 141 |
ABBREVIATION LIST | 143 |
| 147 | |
| 149 | |
Citi izdevumi - Skatīt visu
Turbo Codes: Desirable and Designable Alexandre Giulietti,Bruno Bougard,Liesbet Van Der Perre Ierobežota priekšskatīšana - 2012 |
Turbo Codes Alexandre Giulietti,Bruno Bougard,Liesbet Van Der Perre Priekšskatījums nav pieejams - 2003 |
Turbo Codes: Desirable and Designable Alexandre Giulietti,Bruno Bougard,Liesbet Van Der Perre Priekšskatījums nav pieejams - 2003 |
Bieži izmantoti vārdi un frāzes
3GPP application array AWGN block codes block size block turbo codes branch metrics BTC decoder channel coding Chapter code rate codec codewords coding gain coding performance collision-free interleaver column complexity computed concatenated convolutional codes convolutional turbo codes Cycle Budget Distribution data rate data transfer decoded bit decoding algorithm deinterleaving encoder energy consumption Equation error extrinsic information extrinsic values Figure half-iteration implementation information bits input latency log-likelihood log-likelihood ratio log-max MAP loop transformations MAP algorithm MAP decoding maximum Mbps memory accesses memory architecture memory hierarchy memory module memory organization methodology mother matrix netlist number of iterations optimization output P(u₁ parallel Parity Matrix parity-check matrix permutation pipeline stage Pr{S₁ probability ratio received sequence recursion S₁ Shannon Limit SISO decoder soft-input soft-output Storage Cycle Budget stored symbols systematic termination throughput trade-off transmitted trellis turbo codes turbo decoder VHDL Viterbi Viterbi algorithm workers