Reconfigurable Computing: Architectures, Tools and Applications: Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, ProceedingsPedro C. Diniz Springer Science & Business Media, 2007. gada 19. marts - 392 lappuses This book constitutes the refereed proceedings of the Third International Workshop on Applied Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007. The 27 full papers and 10 short papers presented together with a late-comer contribution from ARC 2006 are organized in topical sections on architectures, mapping techniques and tools, arithmetic, and applications. |
Saturs
Architectural Exploration of the ADRES CoarseGrained Reconfigurable Array | 1 |
A Configurable Multiported Register File Architecture for Soft Processor Cores | 14 |
Multithreading on CoarseGrained Reconfigurable Architecture | 26 |
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture | 39 |
Partially Reconfigurable PointtoPoint Interconnects in VirtexII Pro FPGAs | 49 |
Systematic Customization of OnChip Crossbar Interconnects | 61 |
Why and How | 73 |
Design of a Reversible PLD Architecture | 85 |
Architectural Exploration of the ADRES CoarseGrained Reconfigurable Array | 1 |
A Configurable Multiported Register File Architecture for Soft Processor Cores | 14 |
Multithreading on CoarseGrained Reconfigurable Architecture | 26 |
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture | 39 |
Partially Reconfigurable PointtoPoint Interconnects in VirtexII Pro FPGAs | 49 |
Systematic Customization of OnChip Crossbar Interconnects | 61 |
Why and How | 73 |
Design of a Reversible PLD Architecture | 85 |
Designing Heterogeneous FPGAs with Multiple SBs | 91 |
Performance Modeling for FPGA Implementations | 97 |
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware | 110 |
Adapting and Automating XILINXs Partial Reconfiguration Flow for Multiple Module Implementations | 122 |
A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions | 130 |
Evaluating VariableGrain Logic Cells Using Heterogeneous Technology Mapping | 142 |
The Implementation of a CoarseGrained Reconfigurable Architecture with Loop Selfpipelining | 155 |
HardwareSoftware Codesign for Embedded Implementation of Neural Networks | 167 |
Current Status and Open Issues | 179 |
About the Importance of Operation Grouping Procedures for Multiple WordLength Architecture Optimizations | 191 |
Switching Activity Models for Power Estimation in FPGA Multipliers | 201 |
A Survey | 214 |
A Parallel Version of the ItohTsujii Multiplicative Inversion Algorithm | 226 |
A Fast Finite Field Multiplier | 238 |
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for ContentBased Image Retrieval | 247 |
Image Processing Architecture for Local Features Computation | 259 |
A Compact Shader for FPGABased Volume Rendering Accelerators | 271 |
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications | 283 |
An Overview | 293 |
Reconfigurable Hardware Acceleration of Canonical Graph Labelling | 302 |
Reconfigurable Computing for Accelerating Protein Folding Simulations | 314 |
Application to the Synthesis of Digital Circuits | 326 |
A Space Variant Mapping Architecture for Reliable Car Segmentation | 337 |
A Hardware SAT Solver Using Nonchronological Backtracking and Clause Recording Without Overheads | 343 |
Searching the Web with an FPGA Based Search Engine | 350 |
An Acceleration Method for Evolutionary Systems Based on Iterated Prisoners Dilemma | 358 |
Real Time Architectures for MovingObjects Tracking | 365 |
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller | 373 |
Multiple Sequence Alignment Using Reconfigurable Computing | 379 |
Simulation of the Dynamic Behavior ofOneDimensional Cellular Automata Using Reconfigurable Computing | 385 |
Designing Heterogeneous FPGAs with Multiple SBs | 91 |
Performance Modeling for FPGA Implementations | 97 |
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware | 110 |
Adapting and Automating XILINXs Partial Reconfiguration Flow for Multiple Module Implementations | 122 |
A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions | 130 |
Evaluating VariableGrain Logic Cells Using Heterogeneous Technology Mapping | 142 |
The Implementation of a CoarseGrained Reconfigurable Architecture with Loop Selfpipelining | 155 |
HardwareSoftware Codesign for Embedded Implementation of Neural Networks | 167 |
Current Status and Open Issues | 179 |
About the Importance of Operation Grouping Procedures for Multiple WordLength Architecture Optimizations | 191 |
Switching Activity Models for Power Estimation in FPGA Multipliers | 201 |
A Survey | 214 |
A Parallel Version of the ItohTsujii Multiplicative Inversion Algorithm | 226 |
A Fast Finite Field Multiplier | 238 |
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for ContentBased Image Retrieval | 247 |
Image Processing Architecture for Local Features Computation | 259 |
A Compact Shader for FPGABased Volume Rendering Accelerators | 271 |
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications | 283 |
An Overview | 293 |
Reconfigurable Hardware Acceleration of Canonical Graph Labelling | 302 |
Reconfigurable Computing for Accelerating Protein Folding Simulations | 314 |
Application to the Synthesis of Digital Circuits | 326 |
A Space Variant Mapping Architecture for Reliable Car Segmentation | 337 |
A Hardware SAT Solver Using Nonchronological Backtracking and Clause Recording Without Overheads | 343 |
Searching the Web with an FPGA Based Search Engine | 350 |
An Acceleration Method for Evolutionary Systems Based on Iterated Prisoners Dilemma | 358 |
Real Time Architectures for MovingObjects Tracking | 365 |
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller | 373 |
Multiple Sequence Alignment Using Reconfigurable Computing | 379 |
Simulation of the Dynamic Behavior ofOneDimensional Cellular Automata Using Reconfigurable Computing | 385 |
Bieži izmantoti vārdi un frāzes
ADRES algorithm amino acids application approach architecture array benchmark Berlin Heidelberg 2007 binary bits bitstream blocks BRAMs calculation circuit clock cycle compiler configuration constraints crossbar data reuse datapath descriptors device elements embedded evaluate evolvable hardware execution FIFO Figure filter FPGA FU FU FU function gate graph IDCT IEEE implementation input instructions interconnects interface iteration label latency LNCS loop loop transformations LUTs matrix MAXMISO memory accesses MJPEG mod f(x mode module multiple multiplicative inverse netlist neural network NIOS II node operation optimization output P.C. Diniz paper parallel partial reconfiguration partition performance platform polynomial processing processor proposed protein reconfigurable computing reconfigurable hardware register file regular expressions SAT solver Section sequence signal simulation smart buffer speculative execution SQNR switching synthesis Table Technology throughput Toffoli gate tool topology variable vector vertex VGLC VHDL VLIW word length write ports Xilinx