Performance Modeling for Computer ArchitectsC. M. Krishna John Wiley & Sons, 1995. gada 14. okt. - 404 lappuses As computers become more complex, the number and complexity of the tasks facing the computer architect have increased. Computer performance often depends in complex way on the design parameters and intuition that must be supplemented by performance studies to enhance design productivity. This book introduces computer architects to computer system performance models and shows how they are relatively simple, inexpensive to implement, and sufficiently accurate for most purposes. It discusses the development of performance models based on queuing theory and probability. The text also shows how they are used to provide quick approximate calculations to indicate basic performance tradeoffs and narrow the range of parameters to consider when determining system configurations. It illustrates how performance models can demonstrate how a memory system is to be configured, what the cache structure should be, and what incremental changes in cache size can have on the miss rate. A particularly deep knowledge of probability theory or any other mathematical field to understand the papers in this volume is not required. |
Saturs
Computer Performance Evaluation Methodology | 20 |
Processor Architecture | 47 |
Amdahls Law Generalized and Some Results | 66 |
The Nonuniform Distribution of InstructionLevel and Machine Parallelism and | 80 |
Classification and Performance Evaluation of Instruction Buffering Techniques | 94 |
Characterization of Branch and Data Dependencies in Programs for Evaluating | 104 |
Optimal Pipelining | 121 |
94 | 125 |
An Accurate and Efficient Performance Analysis Technique for Multiprocessor | 232 |
Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling | 240 |
Analysis of Multiprocessors with Private Cache Memories | 252 |
Main Memory Models | 261 |
Performance of ProcessorMemory Interconnections for Multiprocessors | 275 |
General Model for Memory Interference in Multiprocessors and Mean Value Analysis | 285 |
A Performance Study | 302 |
Optimal Design of Multilevel Storage Hierarchies | 318 |
Modeling and Optimization | 131 |
Cache Memory Models | 141 |
An Analytical Cache Model | 171 |
Modeling Live and Dead Lines in Cache Memory Systems | 203 |
Optimal Partitioning of Cache Memory | 217 |
Disk and Disk Cache Systems | 331 |
A ThroughputDriven | 345 |
Synchronized Disk Interleaving | 358 |
An Analytic Performance Model of Disk Arrays | 379 |
Bieži izmantoti vārdi un frāzes
algorithm allocation Amdahl Amdahl's Law analysis analytic model approximation Architecture assume assumption average number bandwidth behavior benchmark block size buffer bytes cache memory cache miss cache miss ratio computer systems control unit crossbar curves cycle delay delta network dependent device disk arrays distribution effect equation error estimate example execution factor footprint function given IEEE IEEE Trans increases instruction instruction-level parallelism interleaved latency live lines load LRU replacement main memory Markov Markov chain measured memory module miss rate miss-rate multiple multiprocessor multiprogramming node number of processors number of segments obtained operations optimal overhead parallel parameters percent pipeline prediction prefetch Prob probability problem Proc PU policy queueing models queueing networks random reconnection reduce references reload transient simulation results speedup statistics superpipelined superscalar synchronized techniques throughput tion trace utilization values variables vector workload write