Software Synthesis from Dataflow GraphsSpringer Science & Business Media, 1996. gada 31. maijs - 190 lappuses Software Synthesis from Dataflow Graphs addresses the problem of generating efficient software implementations from applications specified as synchronous dataflow graphs for programmable digital signal processors (DSPs) used in embedded real- time systems. The advent of high-speed graphics workstations has made feasible the use of graphical block diagram programming environments by designers of signal processing systems. A particular subset of dataflow, called Synchronous Dataflow (SDF), has proven efficient for representing a wide class of unirate and multirate signal processing algorithms, and has been used as the basis for numerous DSP block diagram-based programming environments such as the Signal Processing Workstation from Cadence Design Systems, Inc., COSSAP from Synopsys® (both commercial tools), and the Ptolemy environment from the University of California at Berkeley. A key property of the SDF model is that static schedules can be determined at compile time. This removes the overhead of dynamic scheduling and is thus useful for real-time DSP programs where throughput requirements are often severe. Another constraint that programmable DSPs for embedded systems have is the limited amount of on-chip memory. Off-chip memory is not only expensive but is also slower and increases the power consumption of the system; hence, it is imperative that programs fit in the on-chip memory whenever possible. Software Synthesis from Dataflow Graphs reviews the state-of-the-art in constructing static, memory-optimal schedules for programs expressed as SDF graphs. Code size reduction is obtained by the careful organization of loops in the target code. Data buffering is optimized by constructing the loop hierarchy in provably optimal ways for many classes of SDF graphs. The central result is a uniprocessor scheduling framework that provably synthesizes the most compact looping structures, called single appearance schedules, for a certain class of SDF graphs. In addition, algorithms and heuristics are presented that generate single appearance schedules optimized for data buffering usage. Numerous practical examples and extensive experimental data are provided to illustrate the efficacy of these techniques. |
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Citi izdevumi - Skatīt visu
Software Synthesis from Dataflow Graphs Shuvra S. Bhattacharyya,Praveen K. Murthy,Edward A. Lee Ierobežota priekšskatīšana - 2012 |
Software Synthesis from Dataflow Graphs Shuvra S. Bhattacharyya,Praveen K. Murthy,Edward A. Lee Priekšskatījums nav pieejams - 2011 |
Software Synthesis from Dataflow Graphs Shuvra S. Bhattacharyya,Praveen K. Murthy,Edward A. Lee Priekšskatījums nav pieejams - 2011 |
Bieži izmantoti vārdi un frāzes
actors B₁ actors G actors in G adjacent pair APGAN APGAN instance applied blocking factor BMLB schedule buffer memory requirement compilers computation graph connected SDF graph consistent SDF graph construct contained coprime corresponding dataflow define del(e delayless denote dependence graph directed multigraph easily verified edge in G example filterbank firing GDPPO graph in Figure heuristic input edge introduces a cycle invocation sequence iterands iteration count Lemma loop fusion looped schedule loose interdependence algorithm max_tokens minimal multigraph NP-complete number of tokens optimal periodic schedule positive integer proper clustering condition random graphs repetitions vector RPMC S₁ sample rate sample rate conversion satisfies the proper schedule for G schedule loop scheduling algorithm SDF graph G single appearance schedule snk(e strongly connected component subindependent partition subroutine Suppose that G techniques Theorem tightly interdependent component topological sort v₁ valid schedule valid single appearance vertex Z₁ Z₂
Populāri fragmenti
182. lappuse - SISAL: Streams and Iteration in a Single Assignment Language, Language Reference Manual Version 1.2.
183. lappuse - Pino, S. Ha, EA Lee, and JT Buck. Software synthesis for DSP using Ptolemy.
183. lappuse - PK Murthy. SS Bhattacharyya. and EA Lee, "Combined code and data minimization for synchronous dataflow programs," Journal of Formal Methods in System Design, July 1997.
Atsauces uz šo grāmatu
Modeling Embedded Systems and SoC's: Concurrency and Time in Models of ... Axel Jantsch Priekšskatījums nav pieejams - 2004 |