The Student's Guide to VHDLThe Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses. Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised. In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects. |
No grāmatas satura
1.5. rezultāts no 72.
viii. lappuse
Bits 47 Standard Logic 48 Condition Conversion 49 2.3 Type Classification 50 2.3.1 Subtypes 51 2.3.2 Type Qualification 53 2.3.3 Type Conversion 53 2.4 Attributes of Scalar Types 54 2.5 Expressions and Predefined Operations 57 Exercises ...
Bits 47 Standard Logic 48 Condition Conversion 49 2.3 Type Classification 50 2.3.1 Subtypes 51 2.3.2 Type Qualification 53 2.3.3 Type Conversion 53 2.4 Attributes of Scalar Types 54 2.5 Expressions and Predefined Operations 57 Exercises ...
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... and Parameters 274 8.2.1 Resolved Ports 276 8.2.2 Driving Value Attribute 279 8.2.3 Resolved Signal Parameters 280 Exercises 281 9 Predefined and Standard Packages 9.1 The Predefined Packages standard and env 287 9.2 IEEE Standard ...
... and Parameters 274 8.2.1 Resolved Ports 276 8.2.2 Driving Value Attribute 279 8.2.3 Resolved Signal Parameters 280 Exercises 281 9 Predefined and Standard Packages 9.1 The Predefined Packages standard and env 287 9.2 IEEE Standard ...
xii. lappuse
15.2.2 Synthesizing and Implementing the Alarm Clock 433 Exercises 435 A Standard Packages 437 A.1 The Predefined Package standard 437 A.2 The Predefined Package env 441 A.3 The Predefined Package textio 441 A.4 Standard VHDL ...
15.2.2 Synthesizing and Implementing the Alarm Clock 433 Exercises 435 A Standard Packages 437 A.1 The Predefined Package standard 437 A.2 The Predefined Package env 441 A.3 The Predefined Package textio 441 A.4 Standard VHDL ...
xiv. lappuse
Chapter 8 deals with the important topic of resolved signals, and Chapter 9 describes a number of predefined and standard packages for use in VHDL designs. The third group of chapters covers advanced modeling features in VHDL.
Chapter 8 deals with the important topic of resolved signals, and Chapter 9 describes a number of predefined and standard packages for use in VHDL designs. The third group of chapters covers advanced modeling features in VHDL.
35. lappuse
An example of an integer type is the predefined type integer, which includes all the whole numbers representable on a particular host computer. The language standard requires that the type integer include at least the numbers ...
An example of an integer type is the predefined type integer, which includes all the whole numbers representable on a particular host computer. The language standard requires that the type integer include at least the numbers ...
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Saturs
| 1 | |
| 31 | |
| 65 | |
Chapter 4 Composite Data Types and Operations | 95 |
Chapter 5 Basic Modeling Constructs | 135 |
Chapter 6 Subprograms | 201 |
Chapter 7 Packages and Use Clauses | 239 |
Chapter 8 Resolved Signals | 261 |
Chapter 12 Components and Configurations | 335 |
Chapter 13 Generate Statements | 359 |
Chapter 14 Design for Synthesis | 375 |
System Design Using the Gumnut Core 413 | 413 |
Appendix A Standard Packages | 437 |
Appendix B VHDL Syntax | 461 |
Appendix C Answers to Exercises | 479 |
References | 497 |
Chapter 9 Predefined and Standard Packages | 287 |
Chapter 10 Aliases | 315 |
Chapter 11 Generic Constants | 325 |
Index | 499 |
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actual alias allows alternative applied architecture body array assertion association attribute begin behavioral bit_vector boolean called changes Chapter character choices clause clock complex component condition configuration connected constant constrained contains conversion corresponding count defined delay described determine digit downto driver elements end process entity entity declaration example executed expression false function function function identifier implementation index range indication initial inout input instance instantiation instruction integer label literal logic loop memory natural Note object operand operations output package parameter port map predefined procedure range record refer represent reset resolved result selected shown signal assignment signed simulation specify standard statement std_ulogic string structural subtype syntax rule synthesis tool true unit unsigned variable vector versions VHDL wait width write
Bibliogrāfiskā informācija
| Nosaukums | The Student's Guide to VHDL |
| Autors | Peter J. Ashenden |
| Izdevums: | 2, pārstrādāts |
| Izdevējs | Elsevier, 2008 |
| ISBN | 0080948553, 9780080948553 |
| Apjoms | 528 lappuses |
| Eksportēt avotu | BiBTeX EndNote RefMan |