The Student's Guide to VHDLElsevier, 2008. gada 1. jūl. - 528 lappuses The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses.Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised. In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects. |
No grāmatas satura
1.–5. rezultāts no 88.
viii. lappuse
... Logic Arrays 107 String and Bit-String Literals 108 4.2.2 Unconstrained Array Element Types 109 4.2.3 Unconstrained Array Ports 111 Array Operations and Referencing 114 4.3.1 Logical Operators 114 4.3.2 Shift Operators 116 4.3.3 ...
... Logic Arrays 107 String and Bit-String Literals 108 4.2.2 Unconstrained Array Element Types 109 4.2.3 Unconstrained Array Ports 111 Array Operations and Referencing 114 4.3.1 Logical Operators 114 4.3.2 Shift Operators 116 4.3.3 ...
x. lappuse
... Logic System 295 Standard Integer Numeric Packages Package Summary 307 Operator Overloading Summary 307 Conversion Function Summary 309 298 290 Strength Reduction Function Summary 311 312 315 10.2 Aliases for Non-Data Items 320 ...
... Logic System 295 Standard Integer Numeric Packages Package Summary 307 Operator Overloading Summary 307 Conversion Function Summary 309 298 290 Strength Reduction Function Summary 311 312 315 10.2 Aliases for Non-Data Items 320 ...
xi. lappuse
... Logic 380 14.5 Modeling Sequential Logic 383 14.5.1 Modeling Edge-Triggered Logic 384 14.5.2 Level-Sensitive Logic and Inferring Storage 392 14.5.3 Modeling State Machines 394 14.6 Modeling Memories 396 14.7 Synthesis Attributes 400 ...
... Logic 380 14.5 Modeling Sequential Logic 383 14.5.1 Modeling Edge-Triggered Logic 384 14.5.2 Level-Sensitive Logic and Inferring Storage 392 14.5.3 Modeling State Machines 394 14.6 Modeling Memories 396 14.7 Synthesis Attributes 400 ...
xii. lappuse
... Logic System Package 446 A.6 Standard Integer Numeric Packages 450 A.6.1 The numeric_bit Package 450 A.6.2 The numeric_std Package 456 A.6.3 The numeric_bit_unsigned Package 457 A.6.4 The numeric_std_unsigned Package 459 B VHDL Syntax ...
... Logic System Package 446 A.6 Standard Integer Numeric Packages 450 A.6.1 The numeric_bit Package 450 A.6.2 The numeric_std Package 456 A.6.3 The numeric_bit_unsigned Package 457 A.6.4 The numeric_std_unsigned Package 459 B VHDL Syntax ...
2. lappuse
... logic system, such as temporal logic. Formal verification also requires a mathematical definition of the meaning of the modeling language or notation used to describe a design. The process of 1.2 1.2.1 verification involves application ...
... logic system, such as temporal logic. Formal verification also requires a mathematical definition of the meaning of the modeling language or notation used to describe a design. The process of 1.2 1.2.1 verification involves application ...
Saturs
1 | |
31 | |
65 | |
Chapter 4 Composite Data Types and Operations | 95 |
Chapter 5 Basic Modeling Constructs | 135 |
Chapter 6 Subprograms | 201 |
Chapter 7 Packages and Use Clauses | 239 |
Chapter 8 Resolved Signals | 261 |
Chapter 12 Components and Configurations | 335 |
Chapter 13 Generate Statements | 359 |
Chapter 14 Design for Synthesis | 375 |
System Design Using the Gumnut Core 413 | 413 |
Appendix A Standard Packages | 437 |
Appendix B VHDL Syntax | 461 |
Appendix C Answers to Exercises | 479 |
References | 497 |
Chapter 9 Predefined and Standard Packages | 287 |
Chapter 10 Aliases | 315 |
Chapter 11 Generic Constants | 325 |
Index | 499 |
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actual alias allows alternative applied architecture body array assertion association attribute begin behavioral bit_vector boolean called changes Chapter character choices clause clock complex component condition configuration connected constant constrained contains conversion corresponding count defined delay described determine digit downto driver elements end process entity entity declaration example executed expression false function function function identifier implementation index range indication initial inout input instance instantiation instruction integer label literal logic loop memory natural Note object operand operations output package parameter port map predefined procedure range record refer represent reset resolved result selected shown signal assignment signed simulation specify standard statement std_ulogic string structural subtype syntax rule synthesis tool true unit unsigned variable vector versions VHDL wait width write