The Student's Guide to VHDLElsevier, 2008. gada 1. jūl. - 528 lappuses The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses.Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised. In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects. |
No grāmatas satura
1.–5. rezultāts no 39.
vii. lappuse
... 2.2.1 Type Declarations 34 2.2.2 Integer Types 35 2.2.3 Floating-Point Types 38 2.2.4 Physical Types 39 Time 42 2.2.5 Enumeration Types 43 Characters 44 Booleans 46 Bits 47 Standard Logic 48 Condition Conversion 49 2.3 Type vii Contents.
... 2.2.1 Type Declarations 34 2.2.2 Integer Types 35 2.2.3 Floating-Point Types 38 2.2.4 Physical Types 39 Time 42 2.2.5 Enumeration Types 43 Characters 44 Booleans 46 Bits 47 Standard Logic 48 Condition Conversion 49 2.3 Type vii Contents.
viii. lappuse
Peter J. Ashenden. Bits 47 Standard Logic 48 Condition Conversion 49 2.3 Type Classification 50 2.3.1 Subtypes 51 2.3 ... Conversions 121 4.4 4.3.8 Arrays in Case Statements 124 4.3.9 Matching Case viii Contents.
Peter J. Ashenden. Bits 47 Standard Logic 48 Condition Conversion 49 2.3 Type Classification 50 2.3.1 Subtypes 51 2.3 ... Conversions 121 4.4 4.3.8 Arrays in Case Statements 124 4.3.9 Matching Case viii Contents.
x. lappuse
... Summary 307 Conversion Function Summary 309 298 290 Strength Reduction Function Summary 311 312 315 10.2 Aliases for Non-Data Items 320 Exercises 323 239 261 287 315 11 12 13 14 15 Generic Constants 325 11.1 Generic x Contents.
... Summary 307 Conversion Function Summary 309 298 290 Strength Reduction Function Summary 311 312 315 10.2 Aliases for Non-Data Items 320 Exercises 323 239 261 287 315 11 12 13 14 15 Generic Constants 325 11.1 Generic x Contents.
4. lappuse
... convert the scaled value to a decimal string; write the string to the display output corresponding to this input; end loop; wait for 10 ms; end loop; At this top level of abstraction, the structure of a system may be described as an ...
... convert the scaled value to a decimal string; write the string to the display output corresponding to this input; end loop; wait for 10 ms; end loop; At this top level of abstraction, the structure of a system may be described as an ...
24. lappuse
... converted to the equivalent binary value. The number of bits in the string is the minimal number needed to represent the value. Some examples are D"23" -- equivalent to B"10111" D"64" -- equivalent to B"1000000" 24 Chapter 1 ...
... converted to the equivalent binary value. The number of bits in the string is the minimal number needed to represent the value. Some examples are D"23" -- equivalent to B"10111" D"64" -- equivalent to B"1000000" 24 Chapter 1 ...
Saturs
1 | |
31 | |
65 | |
Chapter 4 Composite Data Types and Operations | 95 |
Chapter 5 Basic Modeling Constructs | 135 |
Chapter 6 Subprograms | 201 |
Chapter 7 Packages and Use Clauses | 239 |
Chapter 8 Resolved Signals | 261 |
Chapter 12 Components and Configurations | 335 |
Chapter 13 Generate Statements | 359 |
Chapter 14 Design for Synthesis | 375 |
System Design Using the Gumnut Core 413 | 413 |
Appendix A Standard Packages | 437 |
Appendix B VHDL Syntax | 461 |
Appendix C Answers to Exercises | 479 |
References | 497 |
Chapter 9 Predefined and Standard Packages | 287 |
Chapter 10 Aliases | 315 |
Chapter 11 Generic Constants | 325 |
Index | 499 |
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actual alias allows alternative applied architecture body array assertion association attribute begin behavioral bit_vector boolean called changes Chapter character choices clause clock complex component condition configuration connected constant constrained contains conversion corresponding count defined delay described determine digit downto driver elements end process entity entity declaration example executed expression false function function function identifier implementation index range indication initial inout input instance instantiation instruction integer label literal logic loop memory natural Note object operand operations output package parameter port map predefined procedure range record refer represent reset resolved result selected shown signal assignment signed simulation specify standard statement std_ulogic string structural subtype syntax rule synthesis tool true unit unsigned variable vector versions VHDL wait width write