The Student's Guide to VHDL
Elsevier, 2008. gada 1. jūl. - 528 lappuses
The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses.
Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised.
In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects.
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Chapter 12 Components and Configurations
Chapter 13 Generate Statements
Chapter 14 Design for Synthesis
System Design Using the Gumnut Core 413
Appendix A Standard Packages
Appendix B VHDL Syntax
Appendix C Answers to Exercises
Chapter 9 Predefined and Standard Packages
Chapter 10 Aliases
Chapter 11 Generic Constants
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actual alias allows alternative applied architecture body array assertion association attribute begin behavioral bit_vector boolean called changes Chapter character choices clause clock complex component condition configuration connected constant constrained contains conversion corresponding count defined delay described determine digit downto driver elements end process entity entity declaration example executed expression false function function function identifier implementation index range indication initial inout input instance instantiation instruction integer label literal logic loop memory natural Note object operand operations output package parameter port map predefined procedure range record refer represent reset resolved result selected shown signal assignment signed simulation specify standard statement std_ulogic string structural subtype syntax rule synthesis tool true unit unsigned variable vector versions VHDL wait width write