Encyclopedia of Computer Science and Technology: Volume 36 - Supplement 21: Artificial Intelligence in Economics and Management to Requirements EngineeringAllen Kent, James G. Williams CRC Press, 1997. gada 14. febr. - 400 lappuses Artificial Intelligence in Economics and Managemetn to Requirements Engineering |
No grāmatas satura
1.5. rezultāts no 84.
19. lappuse
Atvainojiet, šīs lappuses saturs ir ierobežots..
Atvainojiet, šīs lappuses saturs ir ierobežots..
35. lappuse
Atvainojiet, šīs lappuses saturs ir ierobežots..
Atvainojiet, šīs lappuses saturs ir ierobežots..
37. lappuse
Atvainojiet, šīs lappuses saturs ir ierobežots..
Atvainojiet, šīs lappuses saturs ir ierobežots..
43. lappuse
Atvainojiet, šīs lappuses saturs ir ierobežots..
Atvainojiet, šīs lappuses saturs ir ierobežots..
46. lappuse
Atvainojiet, šīs lappuses saturs ir ierobežots..
Atvainojiet, šīs lappuses saturs ir ierobežots..
Saturs
CHECKING AND RESTORING THE CONSISTENCY | 15 |
CONSTRAINT PROGRAMMING | 35 |
DESIGN TECHNOLOGIES FOR LOWPOWER VLSI | 73 |
DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | 97 |
ETHICS IN THE COMPUTER | 139 |
FRACTAL GEOMETRY AND ITS EXPLOITATION | 153 |
HIGHPERFORMANCE COMPUTER ARCHITECTURE | 173 |
HIGHPERFORMANCE DISTRIBUTED COMPUTING | 203 |
INTEGRATED BROADBAND COMMUNICATIONS | 223 |
KNOWLEDGE AND NEURAL HEURISTICS | 241 |
Laita and Luis De Ledesma | 253 |
LOGIC LEVEL MODELING | 281 |
OPEN DISTRIBUTED PROCESSING | 307 |
REQUIREMENTS ENGINEERING | 345 |
Citi izdevumi - Skatīt visu
Encyclopedia of Computer Science and Technology: Volume 36 - Supplement 21 ... Allen Kent,James G. Williams Priekšskatījums nav pieejams - 1997 |
Bieži izmantoti vārdi un frāzes
algorithm applications approach architecture Artificial Intelligence ASIC ATMS behavior Boolean broadband cache Cache Coherence capacitance cells checking chip circuit CMOS communication components concept Conference consistency Constraint Logic Programming Constraint Programming constraint store cycle defined dimension distributed domain environment example execution Expert Systems fault FIGURE formal Formal Verification fractal gate global hardware HPDC IEEE Trans implementation input instruction integration interconnection interface Knowledge Bases Knowledge-Based languages layout logic level Logic Programming logic value memory methods MIMD module multimedia multiway constraint netlist neural network nodes object operations optimization output parallel computing performance pipeline power dissipation problem Proceedings processor protocols Requirements Engineering result RM-ODP rules simulation solution specification speculative execution standard structure superscalar switching activity synthesis Syst techniques tion transistors Validation variables vector Verification VHDL VLSI voltage