Low-Energy FPGAs — Architecture and DesignSpringer Science & Business Media, 2001. gada 30. jūn. - 182 lappuses Low-Energy FPGAs: Architecture and Design is a primary resource for both researchers and practicing engineers in the field of digital circuit design. The book addresses the energy consumption of Field-Programmable Gate Arrays (FPGAs). FPGAs are becoming popular as embedded components in computing platforms. The programmability of the FPGA can be used to customize implementations of functions on an application basis. This leads to performance gains, and enables reuse of expensive silicon. Chapter 1 provides an overview of digital circuit design and FPGAs. Chapter 2 looks at the implication of deep-submicron technology onFPGA power dissipation. Chapter 3 describes the exploration environment to guide and evaluate design decisions. Chapter 4 discusses the architectural optimization process to evaluate the trade-offs between the flexibility of the architecture, and the effect on the performance metrics. Chapter 5 reviews different circuit techniques to reduce the performance overhead of some of the dominant components. Chapter 6 shows methods to configure FPGAs to minimize the programming overhead. Chapter 7 addresses the physical realization of some of the critical components and the final implementation of a specific low-energy FPGA. Chapter 8 compares the prototype array to an equivalent commercial architecture. |
Saturs
INTRODUCTION | 5 |
2 FPGA | 6 |
3 INTERCONNECT ARCHITECTURE | 7 |
4 LOGIC BLOCK ARCHITECTURE | 11 |
5 PROGRAMMING TECHNOLOGY | 13 |
6 COMPUTATION MODEL | 17 |
7 FPGA AS A PERFORMANCE ACCELERATOR | 19 |
8 RESEARCH PROJECTS | 20 |
CIRCUIT TECHNIQUES | 95 |
3 ENERGYDELAY DESIGN SPACE | 96 |
4 LOWSWING SIGNALING | 98 |
5 LOWSWING CIRCUIT | 101 |
6 CLOCK DISTRIBUTION | 105 |
7 CONCLUSION | 110 |
CONFIGURATION ENERGY | 111 |
3 CONFIGURATION TECHNIQUES | 112 |
9 FPGA AND ENERGY CONSUMPTION | 24 |
10 CONCLUSION | 25 |
POWER DISSIPATION IN FPGAS | 27 |
3 IMPACT OF POWER DISSIPATION | 32 |
4 COMPONENTS OF POWER | 34 |
5 CLOCK ENERGY | 38 |
6 CONCLUSION | 40 |
EXPLORATION ENVIRONMENT | 43 |
3 EVALUATION FLOW | 44 |
4 MAPPING | 46 |
5 ARCHITECTURE REPRESENTATION | 47 |
6 PLACEMENT | 50 |
7 ROUTING | 55 |
8 EXTRACTION | 66 |
9 CONCLUSION | 67 |
LOGIC AND INTERCONNECT ARCHITECTURE | 69 |
3 ENERGYDELAY COMPONENTS | 71 |
4 ARCHITECTURAL COMPONENTS | 74 |
5 LOGIC BLOCK | 75 |
6 GOAL OF INTERCONNECT OPTIMIZATION | 81 |
7 INTERCONNECT ARCHITECTURE | 83 |
8 CONCLUSION | 92 |
4 SHIFT REGISTER VERSUS RANDOM ACCESS | 115 |
5 CONFIGURATION ENERGY COMPONENTS | 118 |
6 METHODS TO REDUCE CONFIGURATION ENERGY | 119 |
7 CONCLUSION | 124 |
HARDWARE IMPLEMENTATION | 127 |
3 INTERCONNECT | 131 |
4 TILE LAYOUT | 137 |
5 CONFIGURATION ARCHITECTURE | 139 |
6 FINAL LAYOUT | 142 |
7 FPGA AS AN EMBEDDED UNIT | 143 |
8 CONCLUSION | 149 |
RESULTS | 151 |
3 MEASUREMENT STRATEGY | 153 |
4 MEASURED DATA | 154 |
5 CONCLUSION | 161 |
CONCLUSION | 163 |
3 THIS WORK | 164 |
4 LOOKING AHEAD | 168 |
| 171 | |
| 179 | |
Citi izdevumi - Skatīt visu
Low-Energy FPGAs — Architecture and Design Varghese George,Jan M. Rabaey Ierobežota priekšskatīšana - 2012 |
Low-Energy FPGAs — Architecture and Design Varghese George,Jan M. Rabaey Priekšskatījums nav pieejams - 2012 |
Low-Energy FPGAs - Architecture and Design Varghese George,Jan M Rabaey Priekšskatījums nav pieejams - 2001 |
Bieži izmantoti vārdi un frāzes
3-input LUTs 5-input algorithm antifuse application ASIC chip circuit clock distribution network clock energy components computing configuration bits configuration energy configuration storage connection box cost datapath decoder diffusion capacitance dominant double-edge-triggered energy consumption energy dissipated energy efficiency Energy-Delay Product evaluate Field-Programmable Gate Arrays Figure flexibility flip-flops frequency gate general-purpose processor global GSMT heuristic IKMB implementation improve increase input pin interconnect architecture Level-0 logic block logic capacity LOGIC LOGIC LOGIC lookup table low-energy FPGA LP_PGAII Manhattan distance memory cells Mesh structure method netlist nets nodes optimization output pins path length performance accelerator placement and routing power dissipation programming the FPGA prototype realize reconfigurable reconfigurable computing reduce the number routing channel routing resources routing segments routing switches satellite shift register shown in Fig simulated annealing speed performance SRAM STMicroelectronics switch box Symmetric Mesh architecture target architecture tile total energy tracks transistors VDDH weighted graph Xilinx
Populāri fragmenti
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176. lappuse - Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency," IEEE Journal of Solid-State Circuits, Vol.
172. lappuse - FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. FPGA 1999(1999)59-68 [13] V. Betz and J. Rose: Cluster-Based Logic Blocks for FPGAs: AreaEfficiency vs. Input Sharing and Size. IEEE Custom Integrated Circuits Conference, Santa Clara, CA, (1997) 551-554 [14] Y.
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175. lappuse - Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi, and M. Aoki, "Sub-lV Swing Internal Bus Architecture for Future Low-Power ULSIs," IEEE Journal of SolidState Circuits, vol.
2. lappuse - Wisconsin, has twice taught as a visiting professor in the electrical engineering and computer sciences department at the University of California, Berkeley...
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