Handbook of Semiconductor Manufacturing TechnologyYoshio Nishi, Robert Doering CRC Press, 2017. gada 19. dec. - 1720 lappuses Retaining the comprehensive and in-depth approach that cemented the bestselling first edition's place as a standard reference in the field, the Handbook of Semiconductor Manufacturing Technology, Second Edition features new and updated material that keeps it at the vanguard of today's most dynamic and rapidly growing field. Iconic experts Robert Doering and Yoshio Nishi have again assembled a team of the world's leading specialists in every area of semiconductor manufacturing to provide the most reliable, authoritative, and industry-leading information available. Reflecting rapid progress in many areas, several chapters were heavily revised and updated, and in some cases, rewritten to reflect rapid advances in such areas as interconnect technologies, gate dielectrics, photomask fabrication, IC packaging, and 300 mm wafer fabrication. While no book can be up-to-the-minute with the advances in the semiconductor field, the Handbook of Semiconductor Manufacturing Technology keeps the most important data, methods, tools, and techniques close at hand. |
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2-20. lappuse
... A 130 nm Generation Logic Technology Featuring 70 nm Transistors, Dual VT Transistors and. 6 layers of interconnects.” Tech. Dig. IEEE Int. Interconnect Tech. Conf. (2000): 567–70. 18. Perera, A., B. Smith, N. Cave, M. Sureddin, S ...
... A 130 nm Generation Logic Technology Featuring 70 nm Transistors, Dual VT Transistors and. 6 layers of interconnects.” Tech. Dig. IEEE Int. Interconnect Tech. Conf. (2000): 567–70. 18. Perera, A., B. Smith, N. Cave, M. Sureddin, S ...
Saturs
| 1-1 | |
| 2-1 | |
| 3-1 | |
| 4-1 | |
Chapter 5 Surface Preparation | 5-1 |
Chapter 6 Supercritical Carbon Dioxide in Semiconductor Cleaning | 6-1 |
Chapter 7 Ion Implantation | 7-1 |
Chapter 8 Dopant Diffusion | 8-1 |
Chapter 22 Equipment Reliability | 22-1 |
Chapter 23 Overview of Process Control | 23-1 |
Chapter 24 InLine Metrology | 24-1 |
Chapter 25 InSitu Metrology | 25-1 |
Chapter 26 Yield Modeling | 26-1 |
Chapter 27 Yield Management | 27-1 |
Chapter 28 Electrical Physical and Chemical Characterization | 28-1 |
Chapter 29 Failure Analysis | 29-1 |
Chapter 9 Oxidation and Gate Dielectrics | 9-1 |
Chapter 10 Silicides | 10-1 |
Chapter 11 Rapid Thermal Processing | 11-1 |
Chapter 12 Lowk Dielectrics | 12-1 |
Chapter 13 Chemical Vapor Deposition | 13-1 |
Chapter 14 Atomic Layer Deposition | 14-1 |
Chapter 15 Physical Vapor Deposition | 15-1 |
Chapter 16 Damascene Copper Electroplating | 16-1 |
Chapter 17 ChemicalMechanical Polishing | 17-1 |
Chapter 18 Optical Lithography | 18-1 |
Chapter 19 Photoresist Materials and Processing | 19-1 |
Chapter 20 Photomask Fabrication | 20-1 |
Chapter 21 Plasma Etch | 21-1 |
Chapter 30 Reliability Physics and Engineering | 30-1 |
Chapter 31 Effects of Terrestrial Radiation on Integrated Circuits | 31-1 |
Chapter 32 IntegratedCircuit Packaging | 32-1 |
Chapter 33 300 mm Wafer Fab Logistics and Automated Material Handling Systems | 33-1 |
Chapter 34 Factory Modeling | 34-1 |
Chapter 35 Economics of Semiconductor Manufacturing | 35-1 |
Physical Constants | 35-21 |
Units Conversion | 35-23 |
Standards Commonly Used in Semiconductor Manufacturing | 35-25 |
Acronyms | D-1 |
Index | 1-1 |
Back cover | 1-27 |
Citi izdevumi - Skatīt visu
Handbook of Semiconductor Manufacturing Technology Yoshio Nishi,Robert Doering Ierobežota priekšskatīšana - 2017 |
Handbook of Semiconductor Manufacturing Technology Yoshio Nishi,Robert Doering Ierobežota priekšskatīšana - 2000 |
Handbook of Semiconductor Manufacturing Technology, Second Edition Yoshio Nishi,Robert Doering Priekšskatījums nav pieejams - 2007 |
Bieži izmantoti vārdi un frāzes
achieve addition annealing Appl applications approach atoms barrier beam become channel charge chemical cleaning concentration constant copper crystal defects density depends deposition device dielectric diffusion dopant doping edited effect electrical Electrochem Electron energy Equation et al etch example field Figure film flow formation function gate growth heat higher IEEE implant important improved increase integrated interconnect interface International layer Lett limited lower manufacturing materials measured mechanism metal method nitride oxide oxygen particles pattern performance phase Phys plasma plating polishing polysilicon potential pressure properties range ratio reaction reduced region removal resistance result scaling semiconductor shown shows silicide silicon SiO2 solution step stress structure substrate surface Table Technology temperature thermal thickness thin typically uniformity voltage wafer
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