| William A. Goddard III, Donald Brenner, Sergey Edward Lyshevski, Gerald J Iafrate - 2002 - 830 lapas
...with HighK Gate Dielectrics, 1nternational Electron Devices Meeting, Washington, DC, December 2001. 87. Thompson, S. et aL, An Enhanced 130 nm Generation...Transistors Optimized for High Performance and Low Power at 0.7-1.4 V, 1nternational Electron Devices Meeting, Washington, DC, December 2001. 5 Nanoelectronic... | |
| Yoon-Soo Park, Michael Shur, William Tang - 2002 - 442 lapas
...Logic Technology Requirements Tables. 14Y. Taur and T. Ning, op. cit., pp. 173 - 175. 15 S. Thompson et al., "An Enhanced 130 nm Generation Logic Technology...for High Performance and Low Power at 0.7 - 1.4 V," IEDM Tech. Digest, pp. 257 - 260, Dec. 2001. 16 SF Huang et al., "High Performance 50 nm CMOS Devices... | |
| Mohab Anis, Mohamed I. Elmasry - 2003 - 248 lapas
...Interconnect," in Proceedings of the International Electron Devices Meeting, pp. 249-252,2001. [50] S. Thompson et al., "An Enhanced 130 nm Generation Logic Technology...Optimized for High Performance and Low Power at 0.7 - 1 .4V," in Proceedings of the International Electron Devices Meeting, pp. 257-260, 2001. [51] K.... | |
| Bernhard Wicht - 2003 - 184 lapas
...M. Wei, J. Xu, S. Yang, and M. Bohr, "An Enhanced 130nm Generation Logic Technology Featuring 60nm Transistors Optimized for High Performance and Low Power at 0.7 - 1.4 V," in Technical Digest International Electron Devices Meeting, IEDM. IEEE, Dec. 2001. 21. Tegze P. Haraszti,... | |
| Sergey Edward Lyshevski - 2018 - 912 lapas
...with High-K Gate Dielectrics, International Electron Devices Meeting, Washington, DC, December 2001. [87] Thompson, S. et al., An Enhanced 130 nm Generation...Transistors Optimized for High Performance and Low Power at 0.7-1.4 V, International Electron Devices Meeting, Washington, DC, December 2001. Unimolecular Electronics:... | |
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