Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power DesignSpringer Science & Business Media, 2008. gada 23. janv. - 388 lappuses This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: Design examples illustrate that these techniques can improve energy efficiency by two to three times.
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No grāmatas satura
1.–5. rezultāts no 29.
... fanouts vs. total cell area load for # of fanouts vs. total cell area Gate level netlist Layout Place and route Global routing Cell placement Clock tree synthesis Detailed wire routing Figure 1.1 A typical EDA flow from a high level ...
... fanout-of-4 inverter delay is the delay of an inverter driving a load capacitance that has four times the inverter's input capacitance [38]. This is shown in Figure 2.1. The FO4 metric is not substantially changed by process technology ...
... fanouts. The voltage drop can be avoided by using a complementary PMOS transistor in parallel with the NMOS transistor, but this increases the loading on the inputs, reducing the benefit of PTL. Buffering is needed if the fanins and fanouts ...
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Saturs
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11 | |
Methodology to Optimize Energy of Computation for SOCs | 107 |
Linear Programming for MultiVth and MultiVdd Assignment | 151 |
Power Gating Design Automation | 251 |
Barry Pangrle Srikanth Jadcherla | 281 |
Winning the Power Struggle in an Uncertain | 299 |
DESIGN EXAMPLES | 323 |
Low Power ARM 1136JFS Design | 357 |
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Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low ... David Chinnery,Kurt Keutzer Priekšskatījums nav pieejams - 2008 |
Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low ... David Chinnery,Kurt Keutzer Priekšskatījums nav pieejams - 2010 |
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