Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power DesignSpringer Science & Business Media, 2008. gada 23. janv. - 388 lappuses This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: Design examples illustrate that these techniques can improve energy efficiency by two to three times.
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1.–5. rezultāts no 66.
... critical path may require redoing place and route. After place and route, wire load models for later iterations may be updated based on the resulting layout. There are also verification steps to try to ensure that the final circuit that ...
... critical path delay, at the price of higher power consumption on these paths. To reduce pipeline register delay, the StrongARM used pulse-triggered flip-flops [62] and the XScale used clock pulsed latches [22]. Shorter critical paths ...
... critical paths can increase the speed by 1.5× [18]. Circuitry using only slower complementary static CMOS logic at a tight performance constraint may be 2.0× higher power than circuitry using a high speed logic style to provide timing ...
... critical path delay. With similar microarchitectures, how do ASIC and custom pipelining and parallelism compare? x(n) ... paths are shown in grey. The minimum clock period decreases as the registers break the critical path up into ...
... critical path delay by inserting registers between combinational logic. Glitches may not propagate through pipeline registers, but the switching activity of the combinational logic is otherwise unchanged. Additional pipeline registers ...
Saturs
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11 | |
Methodology to Optimize Energy of Computation for SOCs | 107 |
Linear Programming for MultiVth and MultiVdd Assignment | 151 |
Power Gating Design Automation | 251 |
Barry Pangrle Srikanth Jadcherla | 281 |
Winning the Power Struggle in an Uncertain | 299 |
DESIGN EXAMPLES | 323 |
Low Power ARM 1136JFS Design | 357 |
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Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low ... David Chinnery,Kurt Keutzer Priekšskatījums nav pieejams - 2008 |
Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low ... David Chinnery,Kurt Keutzer Priekšskatījums nav pieejams - 2010 |
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