Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design

Pirmais vāks
Springer Science & Business Media, 2008. gada 23. janv. - 388 lappuses

This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology.

Important topics include:
- Microarchitectural techniques to reduce energy per operation
- Power reduction with timing slack from pipelining
- Analysis of the benefits of using multiple supply and threshold voltages
- Placement techniques for multiple supply voltages
- Verification for multiple voltage domains
- Improved algorithms for gate sizing, and assignment of supply and threshold voltages
- Power gating design automation to reduce leakage
- Relationships among tatistical timing, power analysis, and parametric yield optimization

Design examples illustrate that these techniques can improve energy efficiency by two to three times.

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Atlasītās lappuses

Saturs

78 Summary
186
8 Power Optimization using Multiple Supply Voltages
189
82 Overview of CVS and ECVS
192
a new dualVDD assignment algorithm
196
84 Power savings with CVS and GECVS
199
85 Gate sizing and dualVth assignment
201
86 Power saving with VVS and GVS
211
87 Summary
214

24 ASIC and custom power comparison
15
25 Factors contributing to ASICs being higher power
19
26 Summary
47
3 Pipelining to Reduce the Power
54
31 Introduction
57
32 Pipelining overheads
61
33 Pipelining power and delay model
67
34 ASIC versus custom pipelining
74
35 Other factors affecting the power gap
81
37 Summary
84
4 Voltage Scaling
89
42 Delay
90
43 Switching power
94
44 Short circuit power
95
45 Leakage power
97
46 013um data for total power
99
47 Summary
104
5 Methodology to Optimize Energy of Computation for SOCs
107
52 Problem definition and solution approach
109
53 Optimization methodology
110
54 Experimental results
113
55 Summary
119
6 Linear Programming for Gate Sizing
121
62 Overview of TILOS gate sizing
124
63 Linear programming formulation
126
64 Optimization flow
137
65 Comparison of gate sizing results
140
66 Computation runtime
143
67 Summary
147
7 Linear Programing for MultiVth and MultiVdd Assignment
151
72 Voltage level restoration for multiVdd
155
73 Previous multiVdd and multiVth optimization research
156
74 Optimizing with multiple supply and threshold voltages
160
75 Comparison of multiVdd and multiVth results
167
76 Analysis of power saving with multiVth and multiVdd
171
77 Computational runtimes with multiVdd and multiVth
185
9 Placement for Power Optimization
218
92 Placement basics
221
93 Physical synthesis
226
94 Multiple supply voltage placement
239
95 State of the art
242
96 Summary
246
10 Power Gating Design Automation
251
102 Leakage control techniques
252
103 Power gating design issues
255
104 Coolpower design automation
262
105 Application flows
269
106 Results
272
107 Future work
277
108 Summary
278
11 Verification For Multiple Supply Voltage Designs
281
112 Multiple voltage definitions and scenarios
283
113 Design examples
290
114 Summary
297
12 Winning the Power Struggle in a Uncertain Era
299
122 Process variability and its impact on power
300
123 Parametric yield estimation
303
an overview
305
125 Efficient statistical parametric yield maximization
308
126 Summary
319
13 Pushing ASIC Performance in a Power Envelope
323
131 Introduction
324
133 Design issues in multiVdd ASICs
332
134 Case study
344
135 Summary
353
14 Low Power ARM 1136JFS Design
357
142 Project objective
358
143 Key decisions and implemenations
362
144 Results
377
145 Summary
381
Index
383
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