VHDL:Modular Design and Synthesis of Cores and Systems, Third EditionMcGraw Hill Professional, 2007. gada 22. febr. - 531 lappuses Utilize the Latest VHDL Tools and Techniques for Desigining Embedded Cores, Cutting-Edge Processors, RT Level Components, and Complex Digital Systems Considered and industry classis, VHDL:Modular Design and Synthesis of Cores and Systems has been fully updated to cover methodologies of modern design and the latest uses of VHDL for digital system design. You'll learn how to utilize VHDL to create specific constructs for specific hardware parts, focusing on VHDL's new libraries and packages. The cutting-edge resource explores the design of RT level components, the application of these components in a core-based, and the development of a complete processor design with its hardware and software as a core in a system-on-a-chip(SOC). Filled with over 150 illustrations, VHDL:Modular Design and Synthesis of Cores and Systems features: An entire toolkit for register-transfer level digital system design Testbench development techniques New to this edition: Coverage of the latest uses of VHDL for digital system design, design of IP cores, interactive and self-checking testbench development, and VHDL's new libraries and packages Inside this State-of-the-Art VHDL Design Tool Design Methodology VHDL Overview Structure of VHDL Simulation Model Combinational Circuits Sequential Circuits Testbench Development Control-Data Partitioned Designs Design of RTL Embedded Cores CPU RT Level Design CPU Memory Indtruction Level Testing Software Tools Embedded System Design |
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1.–3. rezultāts no 3.
... arrays of bits. Procedures or functions are only allowed in the context of combinational logic units. Delay and constraint specifications are not allowed in AHPL and assignment of values to buses and registers all occur at the same time ...
... array type declarations and composite type definitions, such as structures or records in programming languages. The DoD document also specified a strongly typed language and strong type checking. 1.4.3.7 Use of Subprograms. The ability ...
... arrays, the std_logic_vector predefined array type in the std_logic package is used. This array type represents is a collection of signals of the std_logic type. The (3 DOWNTO 0) is the range of indices for the vector (3 is the index of ...
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23 | |
Chapter 3 VHDL Constructs for Structure and Hierarchy Descriptions | 77 |
Chapter 4 Concurrent Constructs for RT Level Descriptions | 105 |
Chapter 5 Sequential Constructs for RT Level Descriptions | 123 |
Chapter 6 VHDL Language Utilities and Packages | 161 |
Chapter 7 VHDL Signal Model | 227 |
Chapter 8 Hardware Cores and Models | 273 |
Chapter 9 Core Design Test and Testability | 341 |
Chapter 10 Design Test and Application of a Processor Core | 395 |
Appendixes | 439 |
Index | 523 |
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VHDL:Modular Design and Synthesis of Cores and Systems, Third Edition Zainalabedin Navabi Ierobežota priekšskatīšana - 2007 |
VHDL:Modular Design and Synthesis of Cores and Systems, Third Edition Zainalabedin Navabi Priekšskatījums nav pieejams - 2007 |