VHDL:Modular Design and Synthesis of Cores and Systems, Third Edition

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McGraw Hill Professional, 2007. gada 22. febr. - 531 lappuses
Utilize the Latest VHDL Tools and Techniques for Desigining Embedded Cores, Cutting-Edge Processors, RT Level Components, and Complex Digital Systems

Considered and industry classis, VHDL:Modular Design and Synthesis of Cores and Systems has been fully updated to cover methodologies of modern design and the latest uses of VHDL for digital system design. You'll learn how to utilize VHDL to create specific constructs for specific hardware parts, focusing on VHDL's new libraries and packages.

The cutting-edge resource explores the design of RT level components, the application of these components in a core-based, and the development of a complete processor design with its hardware and software as a core in a system-on-a-chip(SOC). Filled with over 150 illustrations, VHDL:Modular Design and Synthesis of Cores and Systems features:

An entire toolkit for register-transfer level digital system design

Testbench development techniques

New to this edition: Coverage of the latest uses of VHDL for digital system design, design of IP cores, interactive and self-checking testbench development, and VHDL's new libraries and packages

Inside this State-of-the-Art VHDL Design Tool

Design Methodology

VHDL Overview

Structure of VHDL

Simulation Model

Combinational Circuits

Sequential Circuits

Testbench Development

Control-Data Partitioned Designs

Design of RTL Embedded Cores

CPU RT Level Design

CPU Memory Indtruction Level Testing

Software Tools

Embedded System Design

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Atlasītās lappuses

Saturs

Chapter 1 Digital System Design Automation with VHDL
1
Chapter 2 RTL Design with VHDL
23
Chapter 3 VHDL Constructs for Structure and Hierarchy Descriptions
77
Chapter 4 Concurrent Constructs for RT Level Descriptions
105
Chapter 5 Sequential Constructs for RT Level Descriptions
123
Chapter 6 VHDL Language Utilities and Packages
161
Chapter 7 VHDL Signal Model
227
Chapter 8 Hardware Cores and Models
273
Chapter 9 Core Design Test and Testability
341
Chapter 10 Design Test and Application of a Processor Core
395
Appendixes
439
Index
523
Autortiesības

Citi izdevumi - Skatīt visu

VHDL:Modular Design and Synthesis of Cores and Systems, Third Edition
Zainalabedin Navabi
Ierobežota priekšskatīšana - 2007
VHDL:Modular Design and Synthesis of Cores and Systems, Third Edition
Zainalabedin Navabi
Priekšskatījums nav pieejams - 2007

Bieži izmantoti vārdi un frāzes

applied array associated attribute builtin_subprogram becomes BEGIN BIT_VECTOR block body causes chapter circuit clock complete components concurrent condition configuration CONSTANT constructs datapath declaration defined delay described discussed DOWNTO driver elements END ARCHITECTURE END ENTITY END PROCESS ENTITY event example executed expression flip-flop gate guarded hand side hardware IEEE implementation initial input instantiation instruction INTEGER issues language LINE logic LOOP machine memory multiplexer multiplier operators output package parameters placed PORT PORT MAP presented procedure process statement processor range REAL requires reset resolution function resolved result return BOOLEAN return STD_LOGIC_VECTOR SAYEH selected sequential shift shown in Figure shows signal assignment SIGNED simulation specified standard std_logic std_ulogic structure synthesis testbench tion transaction unit UNSIGNED VARIABLE VHDL VHDL code WAIT waveform write

Par autoru (2007)

Zainalabedin Navabi, Ph.D., navabi@ece.neu.edu, is adjunct professor of electrical and computer engineering at Northeastern University and the author of both editions of VDHL: Analysis and Modeling of Digital Systems, published by McGraw-Hill. Since 1981, Dr. Navabi has worked in the design, definition and implementation of hardware description languages and the synthesis and testing of digital systems. He has developed and supervised the development of many HDL-related software packages and tools, and has directed projects in VLSI design, test synthesis, simulation, synthesis, and other aspects of digital system automation. He has served as a consultant for several EDA companies developing HDL based tools and environments. Dr. Navabi is a member of ACM, IEEE, IEEE computer society, and an active participant in IEEE DASC committee that sets standards related to hardware description languages

Bibliogrāfiskā informācija

NosaukumsVHDL:Modular Design and Synthesis of Cores and Systems, Third Edition
AutorsZainalabedin Navabi
Izdevums:3
IzdevējsMcGraw Hill Professional, 2007
ISBN0071508929, 9780071508926
Apjoms531 lappuses
  
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