Multi-Threshold CMOS Digital Circuits: Managing Leakage PowerSpringer Science & Business Media, 2003. gada 31. okt. - 216 lappuses Over the past decade, reducing the dynamic switching power was the main focus in many of the proposed low-power circuit techniques. At that time, the off-state leakage power was negligible compared to dynamic power. However, as technology scales into the deep-submicron regime, the increase in leakage power can no longer be neglected. Soon, the biggest challenge that SoC designers must resolve is the fact that transistors for digital and memory circuits will be more and more leaky as technology generations advance. The semiconductor industry must therefore reduce leakage current in chip designs by two orders of magnitude over the next ten years, or face an interruption in projected chip complexity. Failure to do so would make the mounting leakage current the "big stumbling block to Moore's Law". Furthermore, cooperative approaches between computer-aided design development, circuit design, and technology process must be examined. Multi-Threshold CMOS Digital Circuits Managing Leakage Power discusses the Multi-threshold voltage CMOS (MTCMOS) technology, that has emerged as an increasingly popular technique to control the escalating leakage power, while maintaining high performance. The book addresses the leakage problem in a number of designs for combinational, sequential, dynamic, and current-steering logic. Moreover, computer-aided design methodologies for designing low-leakage integrated circuits are presented. The book give an excellent survey of state-of-the-art techniques presented in the literature as well as proposed designs that minimize leakage power, while achieving high-performance. Multi-Threshold CMOS Digital Circuits Managing Leakage Power is written for students of VLSI design as well as practicing circuit designers, system designers, CAD tool developers and researchers. It assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit design techniques. |
Saturs
INTRODUCTION | 1 |
References | 3 |
LEAKAGE POWER CHALLENGES AND SOLUTIONS | 5 |
22 Power Dissipation in CMOS Digital Circuits | 6 |
23 Impact of Technology Scaling on Leakage Power | 11 |
24 VddVth Design Space | 15 |
25 Total Power Management | 17 |
27 Chapter Summary | 29 |
MTCMOS SEQUENTIAL CIRCUITS | 135 |
53 MTCMOS Balloon Circuit | 136 |
54 Intermittent Power Supply Scheme | 141 |
56 Virtual Rails Clamp VRC Circuit | 143 |
57 Leakage Sneak Paths in MTCMOS Sequential Circuits | 144 |
58 Interfacing MTCMOS and CMOS blocks | 150 |
510 Leakage Feedback Gates | 152 |
511 Chapter Summary | 156 |
References | 31 |
EMBEDDED MTCMOS COMBINATIONAL CIRCUITS | 45 |
33 The Power Minimization Problem | 55 |
34 Algorithms | 57 |
35 Choosing the HighV Value | 65 |
36 Chapter Summary | 67 |
References | 69 |
MTCMOS COMBINATIONAL CIRCUITS USING SLEEP TRANSISTORS | 73 |
43 Variable Breakpoint Switch Level Simulator 1 | 76 |
44 Hierarchical Sizing Based on Mutually Exclusive Discharge Patterns | 79 |
45 Designing HighV Sleep Transistors the Average Current Method 6 | 84 |
46 Drawbacks of Techniques | 89 |
48 Clustering Techniques | 91 |
49 Hybrid Heuristic Techniques | 113 |
410 Virtual Ground Bounce | 119 |
Taking ground bounce into account | 124 |
412 Power Management of Sleep Transistors | 127 |
413 Chapter Summary | 129 |
References | 131 |
References | 159 |
MTCMOS DYNAMIC CIRCUITS | 163 |
Overview | 164 |
63 HSDomino Logic | 168 |
Analysis and Overview | 174 |
65 MTCMOS HSDomino MHSDomino Logic | 180 |
66 Domino Dual Cascode Voltage Switch Logic DDCVSL | 183 |
67 Chapter Summary | 188 |
191 | |
MTCMOS CURRENTSTEERING CIRCUITS | 195 |
72 Introduction | 197 |
First Constraint | 199 |
Second Constraint and the Proposed MTCMOS Design | 201 |
8 Demultiplexer in MTCMOS MCML | 203 |
76 Impact of Using MTCMOS Technology Over MCML Parameters | 206 |
77 Chapter Summary | 212 |
References | 213 |
Citi izdevumi - Skatīt visu
Multi-Threshold CMOS Digital Circuits: Managing Leakage Power Mohab Anis,Mohamed I. Elmasry Ierobežota priekšskatīšana - 2003 |
Multi-Threshold CMOS Digital Circuits: Managing Leakage Power Mohab Anis,Mohamed Elmasry Ierobežota priekšskatīšana - 2012 |
Multi-Threshold CMOS Digital Circuits: Managing Leakage Power Mohab Anis,Mohamed Elmasry Priekšskatījums nav pieejams - 2003 |
Bieži izmantoti vārdi un frāzes
achieved active mode algorithm balloon circuit benchmark capacitance Circuits Conference clock CMOS Circuits CMOS gate CMOS technology controlled NM critical path DDCVS degradation Design Automation Conference Digest of Technical Digital discharge current Domino logic Domino node dynamic and leakage dynamic power Electronics and Design evaluation fanout gate G gradated modulation ground bounce high-Vth devices HS-Domino hybrid heuristic I₁ Ibias IEEE IEEE International Symposium IEEE Journal implementation input vector Integrated Circuits inverter Journal of Solid-State latch leakage current leakage feedback gate leakage power logic block logic gate Low Power Electronics Low-Power MCML MOSFET MTCMOS MTCMOS gate Multi-Threshold N₁ NMOS Optimization output P₁ performance PMOS power dissipation power supply precharge Proc propagation delay reduce resistors scaling simulator sleep transistor sneak leakage paths Solid-State Circuits SP technique speed standby mode subthreshold leakage supply voltage switching Symposium on Low threshold voltage transistor sizes virtual ground
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