Proceedings of the 1993 International Conference on Parallel ProcessingCRC Press, 1993. gada 16. aug. - 384 lappuses This three-volume work presents a compendium of current and seminal papers on parallel/distributed processing offered at the 22nd International Conference on Parallel Processing, held August 16-20, 1993 in Chicago, Illinois. Topics include processor architectures; mapping algorithms to parallel systems, performance evaluations; fault diagnosis, recovery, and tolerance; cube networks; portable software; synchronization; compilers; hypercube computing; and image processing and graphics. Computer professionals in parallel processing, distributed systems, and software engineering will find this book essential to their complete computer reference library. |
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1.–5. rezultāts no 88.
xiii. lappuse
... COMMUNICATION ARCHITECTURE . ( R ) : Dependence Analysis and Architecture Design for Bit - Level Algorithms Weijia Shang and Benjamin W. Wah ( R ) : ATOMIC : A Low - Cost , Very - High - Speed , Local Communication Architecture Danny ...
... COMMUNICATION ARCHITECTURE . ( R ) : Dependence Analysis and Architecture Design for Bit - Level Algorithms Weijia Shang and Benjamin W. Wah ( R ) : ATOMIC : A Low - Cost , Very - High - Speed , Local Communication Architecture Danny ...
xiv. lappuse
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Saturs
GRAPH THEORETIC INTERCONNECTION STRUCTURES 1 I82 | 82 |
SORTINGSEARCHING III183 | 183 |
GRAPH ALGORITHMS II III214 | 214 |
RECONFIGURABLE ARCHITECTURE AND DATABASE APPLICATIONS III235 | 235 |
RESOURCE ALLOCATION AND FAULT TOLERANCE III262 | 262 |
Bieži izmantoti vārdi un frāzes
allocation architecture array background messages binary tree bit-level bitonic bitonic sorter bits block buffer cache coherence cache line cache misses channel checks cluster communication connected copy cube cycle data elements deallocation delay dimension disk disk arrays distributed equation evaluate execution fault fault tolerance Figure footprint graph hardware hit ratios hypercube IEEE implemented input interconnection network iteration latency load loop loop tile mapping matrix memory access memory cache memory module mesh multicast multiple multiprocessor n-SCC nodes number of nodes number of processors operations optimal output packet parallel computers Parallel Processing parameters parity partitioning path performance pipeline prefetching Proc proposed protocol queue RAID5 reference request routing algorithm scalability scheduling scheme sequence shared memory shown SIMD simulation stack star graph strategy structure subcube synchronization task technique Theorem tion topology total number traffic tree update variable vector virtual channels