CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 52.
62. lappuse
... writer of a queue Q ; is mapped onto PR and queue itself is mapped onto SM1 . 3.2 Performance Constraints 3.2.1 Bandwidth Constraint at Shared Memories Arrival rate of read or write requests at a shared memory mod- ule SM , depends on ...
... writer of a queue Q ; is mapped onto PR and queue itself is mapped onto SM1 . 3.2 Performance Constraints 3.2.1 Bandwidth Constraint at Shared Memories Arrival rate of read or write requests at a shared memory mod- ule SM , depends on ...
147. lappuse
Write enable Write Clock Control Column address Row Address Row Rd / Wrt enable Decoder Clock Wordlines Write Data Write Column Logic ( Column Mux and Bitline Drivers ) Memory Core Read enable Clock Column address Read Control Read ...
Write enable Write Clock Control Column address Row Address Row Rd / Wrt enable Decoder Clock Wordlines Write Data Write Column Logic ( Column Mux and Bitline Drivers ) Memory Core Read enable Clock Column address Read Control Read ...
149. lappuse
... write , and read phases and for the whole read column sub - block are shown in Equations 12 , 13 , 14 , and 15 respectively . SrdMur and Swrt Mur indicate the size of the read column mul- tiplexer and write column multiplexer ...
... write , and read phases and for the whole read column sub - block are shown in Equations 12 , 13 , 14 , and 15 respectively . SrdMur and Swrt Mur indicate the size of the read column mul- tiplexer and write column multiplexer ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale