CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 13.
179. lappuse
... wire width very soon becomes wider than the die side . Anyhow , this is the upper bound wires needed to drive the clock net . The capacitance is then Cupper = k . 3 2 D NFF Wwidth ( 9 ) where D is the Manhattan distance from the centre ...
... wire width very soon becomes wider than the die side . Anyhow , this is the upper bound wires needed to drive the clock net . The capacitance is then Cupper = k . 3 2 D NFF Wwidth ( 9 ) where D is the Manhattan distance from the centre ...
180. lappuse
... wires are 2 mm long and 600 nm wide , with a wire pitch of 1.5 μm and shielding ground lines interspersed inbetween the signal lines at the same pitch , and four repeater stages . The original switch decisions , i.e. the routing of ...
... wires are 2 mm long and 600 nm wide , with a wire pitch of 1.5 μm and shielding ground lines interspersed inbetween the signal lines at the same pitch , and four repeater stages . The original switch decisions , i.e. the routing of ...
236. lappuse
... wires , which represent one part of the on - chip communication architecture . However , a state - of - the - art communication architecture , viewed in its entirety , is significantly Permission to make digital or hard copies of all or ...
... wires , which represent one part of the on - chip communication architecture . However , a state - of - the - art communication architecture , viewed in its entirety , is significantly Permission to make digital or hard copies of all or ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale