CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 16.
30. lappuse
... virtual museum or virtual shop applications have become feasible on reconfigurable systems [ 1 , 4 ] . Multimedia applications deal with large sets of data that have to be processed in a little amount of time in order to accomplish ...
... virtual museum or virtual shop applications have become feasible on reconfigurable systems [ 1 , 4 ] . Multimedia applications deal with large sets of data that have to be processed in a little amount of time in order to accomplish ...
83. lappuse
... Virtual ATM Cell Data aggregates like ATM cells [ 3 ] are widely used in many telecom / network applications . These aggregates are used to transfer structured information by means of communication channels . These cells are ...
... Virtual ATM Cell Data aggregates like ATM cells [ 3 ] are widely used in many telecom / network applications . These aggregates are used to transfer structured information by means of communication channels . These cells are ...
98. lappuse
... virtual - to - physical address translations in a set of translation registers ( TRS ) , and using them when necessary instead of going to the data TLB . This paper presents a compiler - based strategy for increasing the effectiveness ...
... virtual - to - physical address translations in a set of translation registers ( TRS ) , and using them when necessary instead of going to the data TLB . This paper presents a compiler - based strategy for increasing the effectiveness ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale