CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 44.
9. lappuse
... variables to be used for calculating the address . The muxes at the top right of the figure use this information to select the appropriate loop variables . The shifters then shift the selected loop variables and the result is ORed and ...
... variables to be used for calculating the address . The muxes at the top right of the figure use this information to select the appropriate loop variables . The shifters then shift the selected loop variables and the result is ORed and ...
89. lappuse
... variables in the clause get the appropriate value based on which satisfying assignment is chosen , add the following constraint for each clause : ac = struct { x : αb , i ; Y : αb , j ; z : αb , k ; } If the inference problem for this ...
... variables in the clause get the appropriate value based on which satisfying assignment is chosen , add the following constraint for each clause : ac = struct { x : αb , i ; Y : αb , j ; z : αb , k ; } If the inference problem for this ...
108. lappuse
... variables . The number of integer variables is O ( MO | | E | ) while the number of binary variables is O ( MO | * | E | 2 ) . The problem is solved using the branch and bound technique of the ILP solver [ 6 ] , which can take ...
... variables . The number of integer variables is O ( MO | | E | ) while the number of binary variables is O ( MO | * | E | 2 ) . The problem is solved using the branch and bound technique of the ILP solver [ 6 ] , which can take ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale