CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 85.
38. lappuse
... values of the candidate variables at the most recent execution of the candidate edge eo . Our solution is , for a given candidate edge and candidate variables , to perform abstract interpretation once for each condition in ( 2 ) ...
... values of the candidate variables at the most recent execution of the candidate edge eo . Our solution is , for a given candidate edge and candidate variables , to perform abstract interpretation once for each condition in ( 2 ) ...
109. lappuse
... values of the SO algorithm . The energy and performance values of the SA algorithm are denoted as the unit valued baseline . The efficient utilization of the SPM by the SO algorithm leads to reductions of upto 65 % in memory energy ...
... values of the SO algorithm . The energy and performance values of the SA algorithm are denoted as the unit valued baseline . The efficient utilization of the SPM by the SO algorithm leads to reductions of upto 65 % in memory energy ...
220. lappuse
... value uy . This transformation process is referred to here as an uniformization process . These two measurements are made to provide initial values ( the discharging time of the processor executing NFI blocks ) for calculating the best ...
... value uy . This transformation process is referred to here as an uniformization process . These two measurements are made to provide initial values ( the discharging time of the processor executing NFI blocks ) for calculating the best ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale