CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 41.
75. lappuse
Transaction Level Modeling : Flows and Use Models Adam Donlin Xilinx Research Labs , 2100 Logic Drive , San Jose , CA 95124 . adam.donlin@xilinx.com Exploiting Polymorphism in HW Design : a Case Study in. ABSTRACT Transaction - level ...
Transaction Level Modeling : Flows and Use Models Adam Donlin Xilinx Research Labs , 2100 Logic Drive , San Jose , CA 95124 . adam.donlin@xilinx.com Exploiting Polymorphism in HW Design : a Case Study in. ABSTRACT Transaction - level ...
242. lappuse
... transaction based Bus Cycle Accurate ( T - BCA ) models have been proposed , which borrow concepts found in the Transaction Level Modeling ( TLM ) domain . More recently , the Cycle Count Accurate at Transaction Boundaries ( CCATB ) ...
... transaction based Bus Cycle Accurate ( T - BCA ) models have been proposed , which borrow concepts found in the Transaction Level Modeling ( TLM ) domain . More recently , the Cycle Count Accurate at Transaction Boundaries ( CCATB ) ...
244. lappuse
... transaction completion which are all features found in high performance bus architectures such as [ 17 ] . OO transaction completion allows slaves to relinquish control of the bus , complete received transactions in any order and then ...
... transaction completion which are all features found in high performance bus architectures such as [ 17 ] . OO transaction completion allows slaves to relinquish control of the bus , complete received transactions in any order and then ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale