CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 79.
118. lappuse
... Task - graph Dynamic Scheduling Task Scheduler DRP Context Scheduler Application ( s ) Task - graph Priority Task Assignment Figure 3 : Design methodology for embedded systems 4.2 Static Phase In this phase there are four main processes ...
... Task - graph Dynamic Scheduling Task Scheduler DRP Context Scheduler Application ( s ) Task - graph Priority Task Assignment Figure 3 : Design methodology for embedded systems 4.2 Static Phase In this phase there are four main processes ...
207. lappuse
... Task Concurrency Management [ 9 ] method focuses on run - time scheduling of tasks on multiprocessor platforms to optimize energy consumption under real - time constraints . The interaction between these tasks is based on low- level ...
... Task Concurrency Management [ 9 ] method focuses on run - time scheduling of tasks on multiprocessor platforms to optimize energy consumption under real - time constraints . The interaction between these tasks is based on low- level ...
211. lappuse
... task and the IZZ task do not need to store blocks locally to interact with each other . They share the tokens in the channel . If the IQ task and the IZZ task need to execute concurrently , then the channel must be able to contain two ...
... task and the IZZ task do not need to store blocks locally to interact with each other . They share the tokens in the channel . If the IQ task and the IZZ task need to execute concurrently , then the channel must be able to contain two ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale