CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 70.
83. lappuse
... structure of the custom cell . Such an implementation is so transferred in the design of the custom ATM cell as it is described in the following . 3.2 Virtual ATM Cell Data aggregates like ATM cells [ 3 ] are widely used in many telecom ...
... structure of the custom cell . Such an implementation is so transferred in the design of the custom ATM cell as it is described in the following . 3.2 Virtual ATM Cell Data aggregates like ATM cells [ 3 ] are widely used in many telecom ...
93. lappuse
... structure from specification include data structure and physical structure . << SoCMbdul e >> Media Processing Chip Dynamic Analsysis Sequence Diagram State Chart Diagram Figure 2. UML modeling flow of specification In the use case ...
... structure from specification include data structure and physical structure . << SoCMbdul e >> Media Processing Chip Dynamic Analsysis Sequence Diagram State Chart Diagram Figure 2. UML modeling flow of specification In the use case ...
102. lappuse
... structure to reduce the per access dTLB energy ; but this would not affect our conclusions as we are interested in the reduction in dTLB accesses and percentage dTLB energy savings . Array accesses are dominant in many applications . In ...
... structure to reduce the per access dTLB energy ; but this would not affect our conclusions as we are interested in the reduction in dTLB accesses and percentage dTLB energy savings . Array accesses are dominant in many applications . In ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale