CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 39.
129. lappuse
... stream rates , or metrics related to the quality of the audio / video output . Alternatively , given certain constrains on the output audio / video quality required and a hardware configuration of the platform , the framework can return ...
... stream rates , or metrics related to the quality of the audio / video output . Alternatively , given certain constrains on the output audio / video quality required and a hardware configuration of the platform , the framework can return ...
130. lappuse
... stream exists . For example , if the archi- tecture shown in Figure 1 is used to implement an MPEG - 2 decoder , then stream objects belonging to the input stream might be single bits . But stream objects belonging to the stream ...
... stream exists . For example , if the archi- tecture shown in Figure 1 is used to implement an MPEG - 2 decoder , then stream objects belonging to the input stream might be single bits . But stream objects belonging to the stream ...
131. lappuse
... stream , as specified by the function C ( t ) , is guaranteed . Clearly , the stream s should be served at both PE1 and PE2 at an average rate which is equal to the long- term average consumption rate of the RTC , and this should also ...
... stream , as specified by the function C ( t ) , is guaranteed . Clearly , the stream s should be served at both PE1 and PE2 at an average rate which is equal to the long- term average consumption rate of the RTC , and this should also ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale