CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 57.
19. lappuse
... step dinD out din M out din dec out step Figure 2. Inc / Dec Architecture 3.1 Describing an Architecture The components themselves are described in a constraint - based language in terms of constraints on signals and a set of rules ...
... step dinD out din M out din dec out step Figure 2. Inc / Dec Architecture 3.1 Describing an Architecture The components themselves are described in a constraint - based language in terms of constraints on signals and a set of rules ...
105. lappuse
1. Memory Object Determination Step 4. Onchip Address Assignment Step 2. Liveness Analysis Step 3. Memory Assignment Step Figure 1 : Workflow of the Scratchpad Overlay Algorithms the first - ones to demonstrate the effectiveness of the ...
1. Memory Object Determination Step 4. Onchip Address Assignment Step 2. Liveness Analysis Step 3. Memory Assignment Step Figure 1 : Workflow of the Scratchpad Overlay Algorithms the first - ones to demonstrate the effectiveness of the ...
173. lappuse
... steps to evaluate the fitness value . To reduce the computation time , we check whether one in- dividual is topologically identical to another individual , and omit the evaluation step if an identical individual has already been eval ...
... steps to evaluate the fitness value . To reduce the computation time , we check whether one in- dividual is topologically identical to another individual , and omit the evaluation step if an identical individual has already been eval ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale