CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 71.
12. lappuse
... Specific Instruction Set Processor . We take a C program and create a target instruction set by compiling to a basic instruction set , from which some instructions are merged , while others discarded . Based on the target instruc- tion ...
... Specific Instruction Set Processor . We take a C program and create a target instruction set by compiling to a basic instruction set , from which some instructions are merged , while others discarded . Based on the target instruc- tion ...
60. lappuse
... Specific Multiprocessors , Kahn Process Networks , Par- titioning 1. INTRODUCTION Typically streaming applications are modeled as either process networks [ 1 , 2 , 3 ] or periodic task graphs in the form of directed acyclic graph ( DAG ) ...
... Specific Multiprocessors , Kahn Process Networks , Par- titioning 1. INTRODUCTION Typically streaming applications are modeled as either process networks [ 1 , 2 , 3 ] or periodic task graphs in the form of directed acyclic graph ( DAG ) ...
82. lappuse
... Specific Class Libraries that consist of a set of application - specific classes . The elements in the Generic Class Library are divided into four groups : • • • Data containers : elements of this group are containers parametric in the ...
... Specific Class Libraries that consist of a set of application - specific classes . The elements in the Generic Class Library are divided into four groups : • • • Data containers : elements of this group are containers parametric in the ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale