CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 72.
242. lappuse
... space early in the design flow . Traditionally , pin- accurate Bus Cycle Accurate ( PA - BCA ) models were used for exploring the communication space . To speed up simulation , transaction based Bus Cycle Accurate ( T - BCA ) models ...
... space early in the design flow . Traditionally , pin- accurate Bus Cycle Accurate ( PA - BCA ) models were used for exploring the communication space . To speed up simulation , transaction based Bus Cycle Accurate ( T - BCA ) models ...
248. lappuse
... space drastically and quickly , and applies a trace - driven simulation technique to the reduced set of design candidates for accurate performance estimation . Since local memory traffic as well as shared memory traffic are involved in ...
... space drastically and quickly , and applies a trace - driven simulation technique to the reduced set of design candidates for accurate performance estimation . Since local memory traffic as well as shared memory traffic are involved in ...
249. lappuse
... space exploration flow . We traverse the design space in an iterative fashion as shown in Figure 2. The body of the iteration loop consists of three main steps . The purpose of the first step is to quickly explore the design subspace of ...
... space exploration flow . We traverse the design space in an iterative fashion as shown in Figure 2. The body of the iteration loop consists of three main steps . The purpose of the first step is to quickly explore the design subspace of ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale