CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 86.
93. lappuse
... shows an example of class diagrams for the structure of a system . The stereotype << SoCModule >> depicts the instance of such class is a component of the target system . Class analysis and class diagram can help us to clarify the ...
... shows an example of class diagrams for the structure of a system . The stereotype << SoCModule >> depicts the instance of such class is a component of the target system . Class analysis and class diagram can help us to clarify the ...
97. lappuse
... shows the number of errors for each component we found in the specification in analysis and modeling phases . The components named " Image Processing " indicate image - processing components that include 2D / 3D graphics , MPEG codec ...
... shows the number of errors for each component we found in the specification in analysis and modeling phases . The components named " Image Processing " indicate image - processing components that include 2D / 3D graphics , MPEG codec ...
211. lappuse
... shows the IZZ task with separate synchronization and data transfer . The IQ task and the IZZ task do not need to store blocks locally to interact with each other . They share the tokens in the channel . If the IQ task and the IZZ task ...
... shows the IZZ task with separate synchronization and data transfer . The IQ task and the IZZ task do not need to store blocks locally to interact with each other . They share the tokens in the channel . If the IQ task and the IZZ task ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale