CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 83.
19. lappuse
... shown in Figure 2 . sel din inc out sel step dinD out din M out din dec out step Figure 2. Inc / Dec Architecture 3.1 Describing an Architecture The components themselves are described in a constraint - based language in terms of ...
... shown in Figure 2 . sel din inc out sel step dinD out din M out din dec out step Figure 2. Inc / Dec Architecture 3.1 Describing an Architecture The components themselves are described in a constraint - based language in terms of ...
148. lappuse
... shown in Equation ( 3 ) . Equation ( 4 ) can be obtained by substituting Equation ( 2 ) in Equation ( 3 ) where WN3 , WP2 , WN1 are widths of N3 , P2 , and N1 respectively , and IIN , IP are the leakage current per unit width for NMOS ...
... shown in Equation ( 3 ) . Equation ( 4 ) can be obtained by substituting Equation ( 2 ) in Equation ( 3 ) where WN3 , WP2 , WN1 are widths of N3 , P2 , and N1 respectively , and IIN , IP are the leakage current per unit width for NMOS ...
150. lappuse
... shown in Equation ( 24 ) . Since each array operational cycle is composed of an operational phase ( opPh ) and a precharge phase ( pchPh ) the average leakage current in an operational cycle can be calculated as shown in Equation ( 25 ) ...
... shown in Equation ( 24 ) . Since each array operational cycle is composed of an operational phase ( opPh ) and a precharge phase ( pchPh ) the average leakage current in an operational cycle can be calculated as shown in Equation ( 25 ) ...
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Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale