CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 39.
62. lappuse
... shared resource = > Waits Bus 1 Application process network Queue Queue Process ! Process3 Queue 3 Architecture Processor 2 Queuing Process3 ) Delays Queue 2 Queue 3 Shared Memory I TH Figure 4 : Synthesis example HI The objective ...
... shared resource = > Waits Bus 1 Application process network Queue Queue Process ! Process3 Queue 3 Architecture Processor 2 Queuing Process3 ) Delays Queue 2 Queue 3 Shared Memory I TH Figure 4 : Synthesis example HI The objective ...
64. lappuse
... shared memories instan- tiated and cost of new links introduced . To illustrate , let us con- sider adjacent process_list of Figure 1 again . While combining partial maps PM [ 2,3 ] ( [ T4 , T3 ] ) and PM [ 4,5 ] ( [ Ts , To ] ) , we ...
... shared memories instan- tiated and cost of new links introduced . To illustrate , let us con- sider adjacent process_list of Figure 1 again . While combining partial maps PM [ 2,3 ] ( [ T4 , T3 ] ) and PM [ 4,5 ] ( [ Ts , To ] ) , we ...
249. lappuse
... shared memories SM_arc2 and SM_arc3 . Memory traces , including both local and shared memory access traces , from all processing elements is one of the inputs to the proposed exploration procedure . After the mapping of function blocks ...
... shared memories SM_arc2 and SM_arc3 . Memory traces , including both local and shared memory access traces , from all processing elements is one of the inputs to the proposed exploration procedure . After the mapping of function blocks ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale