CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 87.
43. lappuse
... represents all data vertices extracted from a SFG . This data distribution can be static or dynamic . In the case of ... represents the dependencies between the operations vertices . The Signal Flow Graph contains | V | = n + 1 vertices ...
... represents all data vertices extracted from a SFG . This data distribution can be static or dynamic . In the case of ... represents the dependencies between the operations vertices . The Signal Flow Graph contains | V | = n + 1 vertices ...
125. lappuse
... represented by a point in the two - dimensional plane with x and y co - ordinates . The x - axis represents the execution time corresponding to the given partition- ing , while the y - axis represents the aggregate HW area . The ...
... represented by a point in the two - dimensional plane with x and y co - ordinates . The x - axis represents the execution time corresponding to the given partition- ing , while the y - axis represents the aggregate HW area . The ...
127. lappuse
... represents the best solutions computed by the KLFM algorithm . Similarly , Fig- ure 8 , Figure 9 , Figure 10 represent the data for graphs with 50 vertices and a CCR of 0.3 , 0.5 , 0.7 respectively . Figs 7-10 represent the data for ...
... represents the best solutions computed by the KLFM algorithm . Similarly , Fig- ure 8 , Figure 9 , Figure 10 represent the data for graphs with 50 vertices and a CCR of 0.3 , 0.5 , 0.7 respectively . Figs 7-10 represent the data for ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale