CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 43.
15. lappuse
resentation depicting the dependency of instructions in an instruction trace , where nodes represent instructions , and directed edges represent dependency . A node has a type that corresponds to the type of instruction it represents ...
resentation depicting the dependency of instructions in an instruction trace , where nodes represent instructions , and directed edges represent dependency . A node has a type that corresponds to the type of instruction it represents ...
40. lappuse
... represent the pred- icates in as 64 - bit numbers , since the set of predicates over k variables is isomorphic to the set of 2 - bit numbers . ( There are k 6 variables in ( 6 ) . ) Conjunction corresponds to bit - wise and ...
... represent the pred- icates in as 64 - bit numbers , since the set of predicates over k variables is isomorphic to the set of 2 - bit numbers . ( There are k 6 variables in ( 6 ) . ) Conjunction corresponds to bit - wise and ...
143. lappuse
... represent knowledge base data . Note the shift in misses from program metadata ( META ) to knowledge base data at around 128K . rectly to the memory system , however , still suffers from ex- tremely constrained performance . Adding a ...
... represent knowledge base data . Note the shift in misses from program metadata ( META ) to knowledge base data at around 128K . rectly to the memory system , however , still suffers from ex- tremely constrained performance . Adding a ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale