CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 10.
77. lappuse
... refinement to an existing reference architecture specification of a hardware subsystem . We constrain the degree of customization applied to the subsystem specification to : • substituting one IP module for another ; adding a small ...
... refinement to an existing reference architecture specification of a hardware subsystem . We constrain the degree of customization applied to the subsystem specification to : • substituting one IP module for another ; adding a small ...
80. lappuse
... refinement flow through the TLM abstractions for UM5 is heavily focused on the CP and CP + T levels . For UM5 , the CP levels can capture the native architecture of the application . Although it is not strictly part of the TLM space ...
... refinement flow through the TLM abstractions for UM5 is heavily focused on the CP and CP + T levels . For UM5 , the CP levels can capture the native architecture of the application . Although it is not strictly part of the TLM space ...
206. lappuse
... refinement of application models towards implementation . By linking application development and implementation . aspects , the technology integrates the specification and design phases in the MPSOC design process . Two design cases ...
... refinement of application models towards implementation . By linking application development and implementation . aspects , the technology integrates the specification and design phases in the MPSOC design process . Two design cases ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
28 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale