CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 27.
94. lappuse
... protocol at the signal level . Component Wrapper Language [ 5 ] has been proposed to model the interface protocol of IP cores compactly and formally . Figure 8 shows an example of CWL description for a full handshake interface protocol ...
... protocol at the signal level . Component Wrapper Language [ 5 ] has been proposed to model the interface protocol of IP cores compactly and formally . Figure 8 shows an example of CWL description for a full handshake interface protocol ...
96. lappuse
... protocol at the signal level . We use CWL description to check the correctness of interface protocol by generating a protocol checker from the CWL2HDL [ 9 ] tool . 4.2 Specification Based Coverage Metrics The specification based ...
... protocol at the signal level . We use CWL description to check the correctness of interface protocol by generating a protocol checker from the CWL2HDL [ 9 ] tool . 4.2 Specification Based Coverage Metrics The specification based ...
250. lappuse
... protocol such as DMA block transfer size and bus priority assignment for a given bus topology [ 5 ] . Compared with ... protocol synthesis of each architecture candidate Once bus topology and memory allocation are determined , bus ...
... protocol such as DMA block transfer size and bus priority assignment for a given bus topology [ 5 ] . Compared with ... protocol synthesis of each architecture candidate Once bus topology and memory allocation are determined , bus ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale