CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 70.
89. lappuse
... problem . The type system and inference problem presented here is very similar to the type system and inference problems in languages such as Haskell . However , the Haskell problem is undecidable in general [ 13 ] . There exist ...
... problem . The type system and inference problem presented here is very similar to the type system and inference problems in languages such as Haskell . However , the Haskell problem is undecidable in general [ 13 ] . There exist ...
105. lappuse
... problem was proven to be NP - complete [ 7 ] . Con- sequently , most of the allocators use a graph coloring [ 5 ] based heuristic . These allocators perform near - optimal allocation for reg- ular architectures with a large number of ...
... problem was proven to be NP - complete [ 7 ] . Con- sequently , most of the allocators use a graph coloring [ 5 ] based heuristic . These allocators perform near - optimal allocation for reg- ular architectures with a large number of ...
123. lappuse
... problem of choosing a suitable granularity for HW - SW partitioning that min- imizes area while meeting timing constraints ; since we consider the problem of minimizing execution time while satisfying HW area constraints , the proposed ...
... problem of choosing a suitable granularity for HW - SW partitioning that min- imizes area while meeting timing constraints ; since we consider the problem of minimizing execution time while satisfying HW area constraints , the proposed ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale