CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 41.
20. lappuse
... PORT is the set of port literals CERT is a certificate , i.e. set of literals ( satisfying the BASE ) present : ( PORT x CERT ) → Boolean ( true if port present in cert ) isSatisfiable : BASE → Boolean ( true if CNF is satisfiable ) ...
... PORT is the set of port literals CERT is a certificate , i.e. set of literals ( satisfying the BASE ) present : ( PORT x CERT ) → Boolean ( true if port present in cert ) isSatisfiable : BASE → Boolean ( true if CNF is satisfiable ) ...
87. lappuse
... port sc_in < T > in ; // output port sc_out < T > out ; in : ' a Queue } out : ' a ( b ) Polymorphic Queue . ( c ) SystemC code . Figure 1 : Port interface for a simple queue . the output of an instruction fetch unit is connected to a ...
... port sc_in < T > in ; // output port sc_out < T > out ; in : ' a Queue } out : ' a ( b ) Polymorphic Queue . ( c ) SystemC code . Figure 1 : Port interface for a simple queue . the output of an instruction fetch unit is connected to a ...
209. lappuse
reAcquireRoom ( port , count ) tryReAcquireRoom ( port , count ) store ( port , offset , vector , size ) releaseData ( port , count ) reAcquireRoom is the blocking acquire function and tryReAcquireRoom is the non - blocking acquire ...
reAcquireRoom ( port , count ) tryReAcquireRoom ( port , count ) store ( port , offset , vector , size ) releaseData ( port , count ) reAcquireRoom is the blocking acquire function and tryReAcquireRoom is the non - blocking acquire ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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