CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.–3. rezultāts no 48.
48. lappuse
... platforms . These factors are the drivers behind the emergence of domain- specific flexible SoC platforms [ 1 ] . The key requirement is for the effective use of platforms via high - level programming models to abstract platform details ...
... platforms . These factors are the drivers behind the emergence of domain- specific flexible SoC platforms [ 1 ] . The key requirement is for the effective use of platforms via high - level programming models to abstract platform details ...
129. lappuse
... platform architecture . This results in a set of traces from which certain parameters- such as the variability in the execution requirements of the application — are computed . These parameters then serve as inputs to analytical models ...
... platform architecture . This results in a set of traces from which certain parameters- such as the variability in the execution requirements of the application — are computed . These parameters then serve as inputs to analytical models ...
207. lappuse
... platform interface . This interface is the target for the mapping of tasks . Previously , several task - level ... platform . interface for implementing applications as communicating hardware and software tasks on a platform ...
... platform interface . This interface is the target for the mapping of tasks . Previously , several task - level ... platform . interface for implementing applications as communicating hardware and software tasks on a platform ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale