CODES+ISSSACM Press, 2004 |
No grāmatas satura
1.3. rezultāts no 84.
20. lappuse
... operation extraction routine . At this point , the designer will see what operations the data path supports . If components are utilized in an unexpected way , the designer must inspect and reformulate the constraints to get the desired ...
... operation extraction routine . At this point , the designer will see what operations the data path supports . If components are utilized in an unexpected way , the designer must inspect and reformulate the constraints to get the desired ...
195. lappuse
... operation latency , and uses it to detect data hazards . However conservative scheduling can be per- formed by assuming the operation latency to be equal to the latency in absence of any bypassing . Although such schedul- ing produces ...
... operation latency , and uses it to detect data hazards . However conservative scheduling can be per- formed by assuming the operation latency to be equal to the latency in absence of any bypassing . Although such schedul- ing produces ...
196. lappuse
... OPERATION TABLE An Operation Table ( OT ) is a binding between an op- eration and the processor resources and registers . An OT lists resources that an operation uses in each cycle of its execution . It also contains information about ...
... OPERATION TABLE An Operation Table ( OT ) is a binding between an op- eration and the processor resources and registers . An OT lists resources that an operation uses in each cycle of its execution . It also contains information about ...
Saturs
Keynote | 1 |
DualPipeline Heterogeneous ASIP Design | 12 |
Fast CycleAccurate Simulation and Instruction Set Generation | 18 |
Autortiesības | |
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algorithm allocation application approach array assignment benchmarks block buffer cache checksum clock compiler components Computer concurrency constraints cosimulator cost cycles data hazard dataflow deadlock decoder design space dTLB dynamic edge embedded systems energy consumption evaluate example execution exploration flash memory function hardware HW/SW IDCT IEEE implementation input instruction set interface iteration latency leakage power livelock logic loop loop fusion mapping memory objects mesochronous methodology multiprocessor node on-chip operation optimal output overhead packet parameters partitioning path performance phase pipeline platform port power consumption problem Proc processor proposed queue reconfigurable register file request requires resource RTOS scenarios scheduling Section shown in Figure signal SIMD simulation solution specification speech recognition Structured ASIC switch synchronization synthesis system-level SystemC Table technique tion type inference type schemes variables Verilog VHDL VLIW XScale